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Searched refs:DMA_CNTL (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsi_dma.c183 dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); in si_dma_start()
185 WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); in si_dma_start()
628 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
630 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
633 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
635 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
644 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
646 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
649 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
651 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
Dsid.h1897 #define DMA_CNTL 0x340b macro
/drivers/gpu/drm/radeon/
Dni_dma.c239 dma_cntl = RREG32(DMA_CNTL + reg_offset); in cayman_dma_resume()
241 WREG32(DMA_CNTL + reg_offset, dma_cntl); in cayman_dma_resume()
Dr600_dma.c160 dma_cntl = RREG32(DMA_CNTL); in r600_dma_resume()
162 WREG32(DMA_CNTL, dma_cntl); in r600_dma_resume()
Dsi.c5954 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5955 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5956 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5957 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
6070 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6071 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6103 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set()
6104 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()
Dnid.h1323 #define DMA_CNTL 0xd02c macro
Dr600.c3620 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state()
3621 WREG32(DMA_CNTL, tmp); in r600_disable_interrupt_state()
3802 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_irq_set()
3871 WREG32(DMA_CNTL, dma_cntl); in r600_irq_set()
Devergreen.c4467 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4468 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state()
4514 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4563 WREG32(DMA_CNTL, dma_cntl); in evergreen_irq_set()
Dsid.h1833 #define DMA_CNTL 0xd02c macro
Devergreend.h1404 #define DMA_CNTL 0xd02c macro
Dr600d.h631 #define DMA_CNTL 0xd02c macro