Home
last modified time | relevance | path

Searched refs:DMA_RB_CNTL (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/radeon/
Dni_dma.c166 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
168 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
171 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
173 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
215 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
246 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); in cayman_dma_resume()
Dr600_dma.c101 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop()
107 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
136 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
170 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
Dni.c1846 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1848 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1853 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1855 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
Dsi.c3880 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3882 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3886 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()
3888 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4047 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4049 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4051 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4053 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
Dnid.h1304 #define DMA_RB_CNTL 0xd000 macro
Dr600.c1703 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_soft_reset()
1705 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_soft_reset()
1834 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_pci_config_reset()
1836 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_pci_config_reset()
Devergreen.c3908 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset()
3910 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset()
4017 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset()
4019 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
Dsid.h1815 #define DMA_RB_CNTL 0xd000 macro
Devergreend.h2618 #define DMA_RB_CNTL 0xd000 macro
Dr600d.h613 #define DMA_RB_CNTL 0xd000 macro
/drivers/gpu/drm/amd/amdgpu/
Dsi_dma.c132 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
134 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
161 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
189 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); in si_dma_start()
Dsid.h1878 #define DMA_RB_CNTL 0x3400 macro