Home
last modified time | relevance | path

Searched refs:DPLL_VCO_ENABLE (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/gma500/
Doaktrail_crtc.c253 if ((temp & DPLL_VCO_ENABLE) == 0) { in oaktrail_crtc_dpms()
259 temp | DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
264 temp | DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
325 if ((temp & DPLL_VCO_ENABLE) != 0) { in oaktrail_crtc_dpms()
327 temp & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
536 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
560 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
562 if (dpll & DPLL_VCO_ENABLE) { in oaktrail_crtc_mode_set()
565 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set()
Dmdfld_intel_display.c277 if (temp & DPLL_VCO_ENABLE) { in mdfld_disable_crtc()
281 temp &= ~(DPLL_VCO_ENABLE); in mdfld_disable_crtc()
334 if ((temp & DPLL_VCO_ENABLE) == 0) { in mdfld_crtc_dpms()
349 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
463 if (temp & DPLL_VCO_ENABLE) { in mdfld_crtc_dpms()
467 temp &= ~(DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
927 if (dpll & DPLL_VCO_ENABLE) { in mdfld_crtc_mode_set()
928 dpll &= ~DPLL_VCO_ENABLE; in mdfld_crtc_mode_set()
994 dpll |= DPLL_VCO_ENABLE; in mdfld_crtc_mode_set()
Dmdfld_device.c263 dpll_val &= ~DPLL_VCO_ENABLE; in mdfld_restore_display_registers()
267 dpll_val &= ~DPLL_VCO_ENABLE; in mdfld_restore_display_registers()
283 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); in mdfld_restore_display_registers()
291 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
307 dpll_val |= DPLL_VCO_ENABLE; in mdfld_restore_display_registers()
Dgma_display.c220 if ((temp & DPLL_VCO_ENABLE) == 0) { in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
306 if ((temp & DPLL_VCO_ENABLE) != 0) { in gma_crtc_dpms()
307 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
586 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { in gma_crtc_restore()
588 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); in gma_crtc_restore()
Dpsb_intel_display.c214 dpll |= DPLL_VCO_ENABLE; in psb_intel_crtc_mode_set()
223 if (dpll & DPLL_VCO_ENABLE) { in psb_intel_crtc_mode_set()
225 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
Dcdv_intel_display.c772 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
782 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
Dpsb_intel_reg.h241 #define DPLL_VCO_ENABLE (1 << 31) macro
/drivers/video/fbdev/intelfb/
Dintelfbhw.h149 #define DPLL_VCO_ENABLE (1 << 31) macro
Dintelfbhw.c1111 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE); in intelfbhw_mode_to_hw()
1402 tmp &= ~DPLL_VCO_ENABLE; in intelfbhw_program_mode()
Dintelfbdrv.c1337 OUTREG(DPLL_A, INREG(DPLL_A) & ~DPLL_VCO_ENABLE); in intelfb_set_par()
/drivers/gpu/drm/i915/
Dintel_display.c1085 cur_state = !!(val & DPLL_VCO_ENABLE); in assert_pll()
1431 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1482 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
6633 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
6650 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
6669 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_prepare_pll()
6672 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
6769 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
6772 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
6978 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
[all …]
Dintel_dpll_mgr.c356 return val & DPLL_VCO_ENABLE; in ibx_pch_dpll_get_hw_state()
Dintel_runtime_pm.c1096 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
Dintel_dp.c510 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
Di915_reg.h3077 #define DPLL_VCO_ENABLE (1 << 31) macro