1 /*
2 * core.h - DesignWare USB3 DRD Core Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #ifndef __DRIVERS_USB_DWC3_CORE_H
20 #define __DRIVERS_USB_DWC3_CORE_H
21
22 #include <linux/device.h>
23 #include <linux/spinlock.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/bitops.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mm.h>
29 #include <linux/debugfs.h>
30 #include <linux/wait.h>
31 #include <linux/workqueue.h>
32
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/otg.h>
36 #include <linux/ulpi/interface.h>
37
38 #include <linux/phy/phy.h>
39
40 #define DWC3_MSG_MAX 500
41
42 /* Global constants */
43 #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
44 #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
45 #define DWC3_EP0_SETUP_SIZE 512
46 #define DWC3_ENDPOINTS_NUM 32
47 #define DWC3_XHCI_RESOURCES_NUM 2
48
49 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
50 #define DWC3_EVENT_BUFFERS_SIZE 4096
51 #define DWC3_EVENT_TYPE_MASK 0xfe
52
53 #define DWC3_EVENT_TYPE_DEV 0
54 #define DWC3_EVENT_TYPE_CARKIT 3
55 #define DWC3_EVENT_TYPE_I2C 4
56
57 #define DWC3_DEVICE_EVENT_DISCONNECT 0
58 #define DWC3_DEVICE_EVENT_RESET 1
59 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
60 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
61 #define DWC3_DEVICE_EVENT_WAKEUP 4
62 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
63 #define DWC3_DEVICE_EVENT_EOPF 6
64 #define DWC3_DEVICE_EVENT_SOF 7
65 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
66 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
67 #define DWC3_DEVICE_EVENT_OVERFLOW 11
68
69 #define DWC3_GEVNTCOUNT_MASK 0xfffc
70 #define DWC3_GEVNTCOUNT_EHB BIT(31)
71 #define DWC3_GSNPSID_MASK 0xffff0000
72 #define DWC3_GSNPSREV_MASK 0xffff
73
74 /* DWC3 registers memory space boundries */
75 #define DWC3_XHCI_REGS_START 0x0
76 #define DWC3_XHCI_REGS_END 0x7fff
77 #define DWC3_GLOBALS_REGS_START 0xc100
78 #define DWC3_GLOBALS_REGS_END 0xc6ff
79 #define DWC3_DEVICE_REGS_START 0xc700
80 #define DWC3_DEVICE_REGS_END 0xcbff
81 #define DWC3_OTG_REGS_START 0xcc00
82 #define DWC3_OTG_REGS_END 0xccff
83
84 /* Global Registers */
85 #define DWC3_GSBUSCFG0 0xc100
86 #define DWC3_GSBUSCFG1 0xc104
87 #define DWC3_GTXTHRCFG 0xc108
88 #define DWC3_GRXTHRCFG 0xc10c
89 #define DWC3_GCTL 0xc110
90 #define DWC3_GEVTEN 0xc114
91 #define DWC3_GSTS 0xc118
92 #define DWC3_GUCTL1 0xc11c
93 #define DWC3_GSNPSID 0xc120
94 #define DWC3_GGPIO 0xc124
95 #define DWC3_GUID 0xc128
96 #define DWC3_GUCTL 0xc12c
97 #define DWC3_GBUSERRADDR0 0xc130
98 #define DWC3_GBUSERRADDR1 0xc134
99 #define DWC3_GPRTBIMAP0 0xc138
100 #define DWC3_GPRTBIMAP1 0xc13c
101 #define DWC3_GHWPARAMS0 0xc140
102 #define DWC3_GHWPARAMS1 0xc144
103 #define DWC3_GHWPARAMS2 0xc148
104 #define DWC3_GHWPARAMS3 0xc14c
105 #define DWC3_GHWPARAMS4 0xc150
106 #define DWC3_GHWPARAMS5 0xc154
107 #define DWC3_GHWPARAMS6 0xc158
108 #define DWC3_GHWPARAMS7 0xc15c
109 #define DWC3_GDBGFIFOSPACE 0xc160
110 #define DWC3_GDBGLTSSM 0xc164
111 #define DWC3_GPRTBIMAP_HS0 0xc180
112 #define DWC3_GPRTBIMAP_HS1 0xc184
113 #define DWC3_GPRTBIMAP_FS0 0xc188
114 #define DWC3_GPRTBIMAP_FS1 0xc18c
115 #define DWC3_GUCTL2 0xc19c
116
117 #define DWC3_VER_NUMBER 0xc1a0
118 #define DWC3_VER_TYPE 0xc1a4
119
120 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
121 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
122
123 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
124
125 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
126
127 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
128 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
129
130 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
131 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
132 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
133 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
134
135 #define DWC3_GHWPARAMS8 0xc600
136 #define DWC3_GFLADJ 0xc630
137
138 /* Device Registers */
139 #define DWC3_DCFG 0xc700
140 #define DWC3_DCTL 0xc704
141 #define DWC3_DEVTEN 0xc708
142 #define DWC3_DSTS 0xc70c
143 #define DWC3_DGCMDPAR 0xc710
144 #define DWC3_DGCMD 0xc714
145 #define DWC3_DALEPENA 0xc720
146
147 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
148 #define DWC3_DEPCMDPAR2 0x00
149 #define DWC3_DEPCMDPAR1 0x04
150 #define DWC3_DEPCMDPAR0 0x08
151 #define DWC3_DEPCMD 0x0c
152
153 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
154
155 /* OTG Registers */
156 #define DWC3_OCFG 0xcc00
157 #define DWC3_OCTL 0xcc04
158 #define DWC3_OEVT 0xcc08
159 #define DWC3_OEVTEN 0xcc0C
160 #define DWC3_OSTS 0xcc10
161
162 /* Bit fields */
163
164 /* Global Debug Queue/FIFO Space Available Register */
165 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
166 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
167 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
168
169 #define DWC3_TXFIFOQ 0
170 #define DWC3_RXFIFOQ 1
171 #define DWC3_TXREQQ 2
172 #define DWC3_RXREQQ 3
173 #define DWC3_RXINFOQ 4
174 #define DWC3_PSTATQ 5
175 #define DWC3_DESCFETCHQ 6
176 #define DWC3_EVENTQ 7
177 #define DWC3_AUXEVENTQ 8
178
179 /* Global RX Threshold Configuration Register */
180 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
181 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
182 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
183
184 /* Global Configuration Register */
185 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
186 #define DWC3_GCTL_U2RSTECN BIT(16)
187 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
188 #define DWC3_GCTL_CLK_BUS (0)
189 #define DWC3_GCTL_CLK_PIPE (1)
190 #define DWC3_GCTL_CLK_PIPEHALF (2)
191 #define DWC3_GCTL_CLK_MASK (3)
192
193 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
194 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
195 #define DWC3_GCTL_PRTCAP_HOST 1
196 #define DWC3_GCTL_PRTCAP_DEVICE 2
197 #define DWC3_GCTL_PRTCAP_OTG 3
198
199 #define DWC3_GCTL_CORESOFTRESET BIT(11)
200 #define DWC3_GCTL_SOFITPSYNC BIT(10)
201 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
202 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
203 #define DWC3_GCTL_DISSCRAMBLE BIT(3)
204 #define DWC3_GCTL_U2EXIT_LFPS BIT(2)
205 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
206 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
207
208 /* Global User Control 1 Register */
209 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
210 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
211
212 /* Global USB2 PHY Configuration Register */
213 #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
214 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
215 #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
216 #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
217 #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
218 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
219 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
220 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
221 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
222 #define USBTRDTIM_UTMI_8_BIT 9
223 #define USBTRDTIM_UTMI_16_BIT 5
224 #define UTMI_PHYIF_16_BIT 1
225 #define UTMI_PHYIF_8_BIT 0
226
227 /* Global USB2 PHY Vendor Control Register */
228 #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
229 #define DWC3_GUSB2PHYACC_BUSY BIT(23)
230 #define DWC3_GUSB2PHYACC_WRITE BIT(22)
231 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
232 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
233 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
234
235 /* Global USB3 PIPE Control Register */
236 #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
237 #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
238 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
239 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
240 #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
241 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
242 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
243 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
244 #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
245 #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
246 #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
247 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
248 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
249 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
250
251 /* Global TX Fifo Size Register */
252 #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
253 #define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff) /* DWC_usb31 only */
254 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
255 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
256
257 /* Global Event Size Registers */
258 #define DWC3_GEVNTSIZ_INTMASK BIT(31)
259 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
260
261 /* Global HWPARAMS0 Register */
262 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
263 #define DWC3_GHWPARAMS0_MODE_GADGET 0
264 #define DWC3_GHWPARAMS0_MODE_HOST 1
265 #define DWC3_GHWPARAMS0_MODE_DRD 2
266 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
267 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
268 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
269 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
270 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
271
272 /* Global HWPARAMS1 Register */
273 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
274 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
275 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
276 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
277 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
278 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
279
280 /* Global HWPARAMS3 Register */
281 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
282 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
283 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
284 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
285 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
286 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
287 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
288 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
289 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
290 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
291 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
292 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
293
294 /* Global HWPARAMS4 Register */
295 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
296 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
297
298 /* Global HWPARAMS6 Register */
299 #define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
300
301 /* Global HWPARAMS7 Register */
302 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
303 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
304
305 /* Global Frame Length Adjustment Register */
306 #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
307 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
308
309 /* Global User Control Register 2 */
310 #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
311
312 /* Device Configuration Register */
313 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
314 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
315
316 #define DWC3_DCFG_SPEED_MASK (7 << 0)
317 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
318 #define DWC3_DCFG_SUPERSPEED (4 << 0)
319 #define DWC3_DCFG_HIGHSPEED (0 << 0)
320 #define DWC3_DCFG_FULLSPEED BIT(0)
321 #define DWC3_DCFG_LOWSPEED (2 << 0)
322
323 #define DWC3_DCFG_NUMP_SHIFT 17
324 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
325 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
326 #define DWC3_DCFG_LPM_CAP BIT(22)
327
328 /* Device Control Register */
329 #define DWC3_DCTL_RUN_STOP BIT(31)
330 #define DWC3_DCTL_CSFTRST BIT(30)
331 #define DWC3_DCTL_LSFTRST BIT(29)
332
333 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
334 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
335
336 #define DWC3_DCTL_APPL1RES BIT(23)
337
338 /* These apply for core versions 1.87a and earlier */
339 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
340 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
341 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
342 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
343 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
344 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
345 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
346
347 /* These apply for core versions 1.94a and later */
348 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
349 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
350
351 #define DWC3_DCTL_KEEP_CONNECT BIT(19)
352 #define DWC3_DCTL_L1_HIBER_EN BIT(18)
353 #define DWC3_DCTL_CRS BIT(17)
354 #define DWC3_DCTL_CSS BIT(16)
355
356 #define DWC3_DCTL_INITU2ENA BIT(12)
357 #define DWC3_DCTL_ACCEPTU2ENA BIT(11)
358 #define DWC3_DCTL_INITU1ENA BIT(10)
359 #define DWC3_DCTL_ACCEPTU1ENA BIT(9)
360 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
361
362 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
363 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
364
365 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
366 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
367 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
368 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
369 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
370 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
371 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
372
373 /* Device Event Enable Register */
374 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
375 #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
376 #define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
377 #define DWC3_DEVTEN_ERRTICERREN BIT(9)
378 #define DWC3_DEVTEN_SOFEN BIT(7)
379 #define DWC3_DEVTEN_EOPFEN BIT(6)
380 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
381 #define DWC3_DEVTEN_WKUPEVTEN BIT(4)
382 #define DWC3_DEVTEN_ULSTCNGEN BIT(3)
383 #define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
384 #define DWC3_DEVTEN_USBRSTEN BIT(1)
385 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
386
387 /* Device Status Register */
388 #define DWC3_DSTS_DCNRD BIT(29)
389
390 /* This applies for core versions 1.87a and earlier */
391 #define DWC3_DSTS_PWRUPREQ BIT(24)
392
393 /* These apply for core versions 1.94a and later */
394 #define DWC3_DSTS_RSS BIT(25)
395 #define DWC3_DSTS_SSS BIT(24)
396
397 #define DWC3_DSTS_COREIDLE BIT(23)
398 #define DWC3_DSTS_DEVCTRLHLT BIT(22)
399
400 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
401 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
402
403 #define DWC3_DSTS_RXFIFOEMPTY BIT(17)
404
405 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
406 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
407
408 #define DWC3_DSTS_CONNECTSPD (7 << 0)
409
410 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
411 #define DWC3_DSTS_SUPERSPEED (4 << 0)
412 #define DWC3_DSTS_HIGHSPEED (0 << 0)
413 #define DWC3_DSTS_FULLSPEED BIT(0)
414 #define DWC3_DSTS_LOWSPEED (2 << 0)
415
416 /* Device Generic Command Register */
417 #define DWC3_DGCMD_SET_LMP 0x01
418 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
419 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
420
421 /* These apply for core versions 1.94a and later */
422 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
423 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
424
425 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
426 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
427 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
428 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
429
430 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
431 #define DWC3_DGCMD_CMDACT BIT(10)
432 #define DWC3_DGCMD_CMDIOC BIT(8)
433
434 /* Device Generic Command Parameter Register */
435 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
436 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
437 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
438 #define DWC3_DGCMDPAR_TX_FIFO BIT(5)
439 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
440 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
441
442 /* Device Endpoint Command Register */
443 #define DWC3_DEPCMD_PARAM_SHIFT 16
444 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
445 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
446 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
447 #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
448 #define DWC3_DEPCMD_CLEARPENDIN BIT(11)
449 #define DWC3_DEPCMD_CMDACT BIT(10)
450 #define DWC3_DEPCMD_CMDIOC BIT(8)
451
452 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
453 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
454 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
455 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
456 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
457 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
458 /* This applies for core versions 1.90a and earlier */
459 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
460 /* This applies for core versions 1.94a and later */
461 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
462 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
463 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
464
465 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
466
467 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
468 #define DWC3_DALEPENA_EP(n) BIT(n)
469
470 #define DWC3_DEPCMD_TYPE_CONTROL 0
471 #define DWC3_DEPCMD_TYPE_ISOC 1
472 #define DWC3_DEPCMD_TYPE_BULK 2
473 #define DWC3_DEPCMD_TYPE_INTR 3
474
475 #define DWC3_DEV_IMOD_COUNT_SHIFT 16
476 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
477 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
478 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
479
480 /* Structures */
481
482 struct dwc3_trb;
483
484 /**
485 * struct dwc3_event_buffer - Software event buffer representation
486 * @buf: _THE_ buffer
487 * @cache: The buffer cache used in the threaded interrupt
488 * @length: size of this buffer
489 * @lpos: event offset
490 * @count: cache of last read event count register
491 * @flags: flags related to this event buffer
492 * @dma: dma_addr_t
493 * @dwc: pointer to DWC controller
494 */
495 struct dwc3_event_buffer {
496 void *buf;
497 void *cache;
498 unsigned length;
499 unsigned int lpos;
500 unsigned int count;
501 unsigned int flags;
502
503 #define DWC3_EVENT_PENDING BIT(0)
504
505 dma_addr_t dma;
506
507 struct dwc3 *dwc;
508 };
509
510 #define DWC3_EP_FLAG_STALLED BIT(0)
511 #define DWC3_EP_FLAG_WEDGED BIT(1)
512
513 #define DWC3_EP_DIRECTION_TX true
514 #define DWC3_EP_DIRECTION_RX false
515
516 #define DWC3_TRB_NUM 256
517
518 /**
519 * struct dwc3_ep - device side endpoint representation
520 * @endpoint: usb endpoint
521 * @pending_list: list of pending requests for this endpoint
522 * @started_list: list of started requests on this endpoint
523 * @wait_end_transfer: wait_queue_head_t for waiting on End Transfer complete
524 * @lock: spinlock for endpoint request queue traversal
525 * @regs: pointer to first endpoint register
526 * @trb_pool: array of transaction buffers
527 * @trb_pool_dma: dma address of @trb_pool
528 * @trb_enqueue: enqueue 'pointer' into TRB array
529 * @trb_dequeue: dequeue 'pointer' into TRB array
530 * @dwc: pointer to DWC controller
531 * @saved_state: ep state saved during hibernation
532 * @flags: endpoint flags (wedged, stalled, ...)
533 * @number: endpoint number (1 - 15)
534 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
535 * @resource_index: Resource transfer index
536 * @interval: the interval on which the ISOC transfer is started
537 * @allocated_requests: number of requests allocated
538 * @queued_requests: number of requests queued for transfer
539 * @name: a human readable name e.g. ep1out-bulk
540 * @direction: true for TX, false for RX
541 * @stream_capable: true when streams are enabled
542 */
543 struct dwc3_ep {
544 struct usb_ep endpoint;
545 struct list_head pending_list;
546 struct list_head started_list;
547
548 wait_queue_head_t wait_end_transfer;
549
550 spinlock_t lock;
551 void __iomem *regs;
552
553 struct dwc3_trb *trb_pool;
554 dma_addr_t trb_pool_dma;
555 struct dwc3 *dwc;
556
557 u32 saved_state;
558 unsigned flags;
559 #define DWC3_EP_ENABLED BIT(0)
560 #define DWC3_EP_STALL BIT(1)
561 #define DWC3_EP_WEDGE BIT(2)
562 #define DWC3_EP_BUSY BIT(4)
563 #define DWC3_EP_PENDING_REQUEST BIT(5)
564 #define DWC3_EP_MISSED_ISOC BIT(6)
565 #define DWC3_EP_END_TRANSFER_PENDING BIT(7)
566 #define DWC3_EP_TRANSFER_STARTED BIT(8)
567
568 /* This last one is specific to EP0 */
569 #define DWC3_EP0_DIR_IN BIT(31)
570
571 /*
572 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
573 * use a u8 type here. If anybody decides to increase number of TRBs to
574 * anything larger than 256 - I can't see why people would want to do
575 * this though - then this type needs to be changed.
576 *
577 * By using u8 types we ensure that our % operator when incrementing
578 * enqueue and dequeue get optimized away by the compiler.
579 */
580 u8 trb_enqueue;
581 u8 trb_dequeue;
582
583 u8 number;
584 u8 type;
585 u8 resource_index;
586 u32 allocated_requests;
587 u32 queued_requests;
588 u32 interval;
589
590 char name[20];
591
592 unsigned direction:1;
593 unsigned stream_capable:1;
594 };
595
596 enum dwc3_phy {
597 DWC3_PHY_UNKNOWN = 0,
598 DWC3_PHY_USB3,
599 DWC3_PHY_USB2,
600 };
601
602 enum dwc3_ep0_next {
603 DWC3_EP0_UNKNOWN = 0,
604 DWC3_EP0_COMPLETE,
605 DWC3_EP0_NRDY_DATA,
606 DWC3_EP0_NRDY_STATUS,
607 };
608
609 enum dwc3_ep0_state {
610 EP0_UNCONNECTED = 0,
611 EP0_SETUP_PHASE,
612 EP0_DATA_PHASE,
613 EP0_STATUS_PHASE,
614 };
615
616 enum dwc3_link_state {
617 /* In SuperSpeed */
618 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
619 DWC3_LINK_STATE_U1 = 0x01,
620 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
621 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
622 DWC3_LINK_STATE_SS_DIS = 0x04,
623 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
624 DWC3_LINK_STATE_SS_INACT = 0x06,
625 DWC3_LINK_STATE_POLL = 0x07,
626 DWC3_LINK_STATE_RECOV = 0x08,
627 DWC3_LINK_STATE_HRESET = 0x09,
628 DWC3_LINK_STATE_CMPLY = 0x0a,
629 DWC3_LINK_STATE_LPBK = 0x0b,
630 DWC3_LINK_STATE_RESET = 0x0e,
631 DWC3_LINK_STATE_RESUME = 0x0f,
632 DWC3_LINK_STATE_MASK = 0x0f,
633 };
634
635 /* TRB Length, PCM and Status */
636 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
637 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
638 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
639 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
640
641 #define DWC3_TRBSTS_OK 0
642 #define DWC3_TRBSTS_MISSED_ISOC 1
643 #define DWC3_TRBSTS_SETUP_PENDING 2
644 #define DWC3_TRB_STS_XFER_IN_PROG 4
645
646 /* TRB Control */
647 #define DWC3_TRB_CTRL_HWO BIT(0)
648 #define DWC3_TRB_CTRL_LST BIT(1)
649 #define DWC3_TRB_CTRL_CHN BIT(2)
650 #define DWC3_TRB_CTRL_CSP BIT(3)
651 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
652 #define DWC3_TRB_CTRL_ISP_IMI BIT(10)
653 #define DWC3_TRB_CTRL_IOC BIT(11)
654 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
655
656 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
657 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
658 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
659 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
660 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
661 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
662 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
663 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
664 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
665
666 /**
667 * struct dwc3_trb - transfer request block (hw format)
668 * @bpl: DW0-3
669 * @bph: DW4-7
670 * @size: DW8-B
671 * @ctrl: DWC-F
672 */
673 struct dwc3_trb {
674 u32 bpl;
675 u32 bph;
676 u32 size;
677 u32 ctrl;
678 } __packed;
679
680 /**
681 * struct dwc3_hwparams - copy of HWPARAMS registers
682 * @hwparams0: GHWPARAMS0
683 * @hwparams1: GHWPARAMS1
684 * @hwparams2: GHWPARAMS2
685 * @hwparams3: GHWPARAMS3
686 * @hwparams4: GHWPARAMS4
687 * @hwparams5: GHWPARAMS5
688 * @hwparams6: GHWPARAMS6
689 * @hwparams7: GHWPARAMS7
690 * @hwparams8: GHWPARAMS8
691 */
692 struct dwc3_hwparams {
693 u32 hwparams0;
694 u32 hwparams1;
695 u32 hwparams2;
696 u32 hwparams3;
697 u32 hwparams4;
698 u32 hwparams5;
699 u32 hwparams6;
700 u32 hwparams7;
701 u32 hwparams8;
702 };
703
704 /* HWPARAMS0 */
705 #define DWC3_MODE(n) ((n) & 0x7)
706
707 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
708
709 /* HWPARAMS1 */
710 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
711
712 /* HWPARAMS3 */
713 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
714 #define DWC3_NUM_EPS_MASK (0x3f << 12)
715 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
716 (DWC3_NUM_EPS_MASK)) >> 12)
717 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
718 (DWC3_NUM_IN_EPS_MASK)) >> 18)
719
720 /* HWPARAMS7 */
721 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
722
723 /**
724 * struct dwc3_request - representation of a transfer request
725 * @request: struct usb_request to be transferred
726 * @list: a list_head used for request queueing
727 * @dep: struct dwc3_ep owning this request
728 * @sg: pointer to first incomplete sg
729 * @num_pending_sgs: counter to pending sgs
730 * @remaining: amount of data remaining
731 * @epnum: endpoint number to which this request refers
732 * @trb: pointer to struct dwc3_trb
733 * @trb_dma: DMA address of @trb
734 * @unaligned: true for OUT endpoints with length not divisible by maxp
735 * @direction: IN or OUT direction flag
736 * @mapped: true when request has been dma-mapped
737 * @started: request is started
738 * @zero: wants a ZLP
739 */
740 struct dwc3_request {
741 struct usb_request request;
742 struct list_head list;
743 struct dwc3_ep *dep;
744 struct scatterlist *sg;
745
746 unsigned num_pending_sgs;
747 unsigned remaining;
748 u8 epnum;
749 struct dwc3_trb *trb;
750 dma_addr_t trb_dma;
751
752 unsigned unaligned:1;
753 unsigned direction:1;
754 unsigned mapped:1;
755 unsigned started:1;
756 unsigned zero:1;
757 };
758
759 /*
760 * struct dwc3_scratchpad_array - hibernation scratchpad array
761 * (format defined by hw)
762 */
763 struct dwc3_scratchpad_array {
764 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
765 };
766
767 /**
768 * struct dwc3 - representation of our controller
769 * @drd_work: workqueue used for role swapping
770 * @ep0_trb: trb which is used for the ctrl_req
771 * @bounce: address of bounce buffer
772 * @scratchbuf: address of scratch buffer
773 * @setup_buf: used while precessing STD USB requests
774 * @ep0_trb_addr: dma address of @ep0_trb
775 * @bounce_addr: dma address of @bounce
776 * @ep0_usb_req: dummy req used while handling STD USB requests
777 * @scratch_addr: dma address of scratchbuf
778 * @ep0_in_setup: one control transfer is completed and enter setup phase
779 * @lock: for synchronizing
780 * @dev: pointer to our struct device
781 * @sysdev: pointer to the DMA-capable device
782 * @xhci: pointer to our xHCI child
783 * @xhci_resources: struct resources for our @xhci child
784 * @ev_buf: struct dwc3_event_buffer pointer
785 * @eps: endpoint array
786 * @gadget: device side representation of the peripheral controller
787 * @gadget_driver: pointer to the gadget driver
788 * @regs: base address for our registers
789 * @regs_size: address space size
790 * @fladj: frame length adjustment
791 * @irq_gadget: peripheral controller's IRQ number
792 * @nr_scratch: number of scratch buffers
793 * @u1u2: only used on revisions <1.83a for workaround
794 * @maximum_speed: maximum speed requested (mainly for testing purposes)
795 * @revision: revision register contents
796 * @dr_mode: requested mode of operation
797 * @current_dr_role: current role of operation when in dual-role mode
798 * @desired_dr_role: desired role of operation when in dual-role mode
799 * @edev: extcon handle
800 * @edev_nb: extcon notifier
801 * @hsphy_mode: UTMI phy mode, one of following:
802 * - USBPHY_INTERFACE_MODE_UTMI
803 * - USBPHY_INTERFACE_MODE_UTMIW
804 * @usb2_phy: pointer to USB2 PHY
805 * @usb3_phy: pointer to USB3 PHY
806 * @usb2_generic_phy: pointer to USB2 PHY
807 * @usb3_generic_phy: pointer to USB3 PHY
808 * @phys_ready: flag to indicate that PHYs are ready
809 * @ulpi: pointer to ulpi interface
810 * @ulpi_ready: flag to indicate that ULPI is initialized
811 * @isoch_delay: wValue from Set Isochronous Delay request;
812 * @u2sel: parameter from Set SEL request.
813 * @u2pel: parameter from Set SEL request.
814 * @u1sel: parameter from Set SEL request.
815 * @u1pel: parameter from Set SEL request.
816 * @num_eps: number of endpoints
817 * @ep0_next_event: hold the next expected event
818 * @ep0state: state of endpoint zero
819 * @link_state: link state
820 * @speed: device speed (super, high, full, low)
821 * @hwparams: copy of hwparams registers
822 * @root: debugfs root folder pointer
823 * @regset: debugfs pointer to regdump file
824 * @test_mode: true when we're entering a USB test mode
825 * @test_mode_nr: test feature selector
826 * @lpm_nyet_threshold: LPM NYET response threshold
827 * @hird_threshold: HIRD threshold
828 * @hsphy_interface: "utmi" or "ulpi"
829 * @connected: true when we're connected to a host, false otherwise
830 * @delayed_status: true when gadget driver asks for delayed status
831 * @ep0_bounced: true when we used bounce buffer
832 * @ep0_expect_in: true when we expect a DATA IN transfer
833 * @has_hibernation: true when dwc3 was configured with Hibernation
834 * @sysdev_is_parent: true when dwc3 device has a parent driver
835 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
836 * there's now way for software to detect this in runtime.
837 * @is_utmi_l1_suspend: the core asserts output signal
838 * 0 - utmi_sleep_n
839 * 1 - utmi_l1_suspend_n
840 * @is_fpga: true when we are using the FPGA board
841 * @pending_events: true when we have pending IRQs to be handled
842 * @pullups_connected: true when Run/Stop bit is set
843 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
844 * @three_stage_setup: set if we perform a three phase setup
845 * @usb3_lpm_capable: set if hadrware supports Link Power Management
846 * @disable_scramble_quirk: set if we enable the disable scramble quirk
847 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
848 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
849 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
850 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
851 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
852 * @lfps_filter_quirk: set if we enable LFPS filter quirk
853 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
854 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
855 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
856 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
857 * disabling the suspend signal to the PHY.
858 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
859 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
860 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
861 * provide a free-running PHY clock.
862 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
863 * change quirk.
864 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
865 * check during HS transmit.
866 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
867 * @tx_de_emphasis: Tx de-emphasis value
868 * 0 - -6dB de-emphasis
869 * 1 - -3.5dB de-emphasis
870 * 2 - No de-emphasis
871 * 3 - Reserved
872 * @dis_metastability_quirk: set to disable metastability quirk.
873 * @imod_interval: set the interrupt moderation interval in 250ns
874 * increments or 0 to disable.
875 */
876 struct dwc3 {
877 struct work_struct drd_work;
878 struct dwc3_trb *ep0_trb;
879 void *bounce;
880 void *scratchbuf;
881 u8 *setup_buf;
882 dma_addr_t ep0_trb_addr;
883 dma_addr_t bounce_addr;
884 dma_addr_t scratch_addr;
885 struct dwc3_request ep0_usb_req;
886 struct completion ep0_in_setup;
887
888 /* device lock */
889 spinlock_t lock;
890
891 struct device *dev;
892 struct device *sysdev;
893
894 struct platform_device *xhci;
895 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
896
897 struct dwc3_event_buffer *ev_buf;
898 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
899
900 struct usb_gadget gadget;
901 struct usb_gadget_driver *gadget_driver;
902
903 struct usb_phy *usb2_phy;
904 struct usb_phy *usb3_phy;
905
906 struct phy *usb2_generic_phy;
907 struct phy *usb3_generic_phy;
908
909 bool phys_ready;
910
911 struct ulpi *ulpi;
912 bool ulpi_ready;
913
914 void __iomem *regs;
915 size_t regs_size;
916
917 enum usb_dr_mode dr_mode;
918 u32 current_dr_role;
919 u32 desired_dr_role;
920 struct extcon_dev *edev;
921 struct notifier_block edev_nb;
922 enum usb_phy_interface hsphy_mode;
923
924 u32 fladj;
925 u32 irq_gadget;
926 u32 nr_scratch;
927 u32 u1u2;
928 u32 maximum_speed;
929
930 /*
931 * All 3.1 IP version constants are greater than the 3.0 IP
932 * version constants. This works for most version checks in
933 * dwc3. However, in the future, this may not apply as
934 * features may be developed on newer versions of the 3.0 IP
935 * that are not in the 3.1 IP.
936 */
937 u32 revision;
938
939 #define DWC3_REVISION_173A 0x5533173a
940 #define DWC3_REVISION_175A 0x5533175a
941 #define DWC3_REVISION_180A 0x5533180a
942 #define DWC3_REVISION_183A 0x5533183a
943 #define DWC3_REVISION_185A 0x5533185a
944 #define DWC3_REVISION_187A 0x5533187a
945 #define DWC3_REVISION_188A 0x5533188a
946 #define DWC3_REVISION_190A 0x5533190a
947 #define DWC3_REVISION_194A 0x5533194a
948 #define DWC3_REVISION_200A 0x5533200a
949 #define DWC3_REVISION_202A 0x5533202a
950 #define DWC3_REVISION_210A 0x5533210a
951 #define DWC3_REVISION_220A 0x5533220a
952 #define DWC3_REVISION_230A 0x5533230a
953 #define DWC3_REVISION_240A 0x5533240a
954 #define DWC3_REVISION_250A 0x5533250a
955 #define DWC3_REVISION_260A 0x5533260a
956 #define DWC3_REVISION_270A 0x5533270a
957 #define DWC3_REVISION_280A 0x5533280a
958 #define DWC3_REVISION_290A 0x5533290a
959 #define DWC3_REVISION_300A 0x5533300a
960 #define DWC3_REVISION_310A 0x5533310a
961
962 /*
963 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
964 * just so dwc31 revisions are always larger than dwc3.
965 */
966 #define DWC3_REVISION_IS_DWC31 0x80000000
967 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31)
968 #define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31)
969
970 enum dwc3_ep0_next ep0_next_event;
971 enum dwc3_ep0_state ep0state;
972 enum dwc3_link_state link_state;
973
974 u16 isoch_delay;
975 u16 u2sel;
976 u16 u2pel;
977 u8 u1sel;
978 u8 u1pel;
979
980 u8 speed;
981
982 u8 num_eps;
983
984 struct dwc3_hwparams hwparams;
985 struct dentry *root;
986 struct debugfs_regset32 *regset;
987
988 u8 test_mode;
989 u8 test_mode_nr;
990 u8 lpm_nyet_threshold;
991 u8 hird_threshold;
992
993 const char *hsphy_interface;
994
995 unsigned connected:1;
996 unsigned delayed_status:1;
997 unsigned ep0_bounced:1;
998 unsigned ep0_expect_in:1;
999 unsigned has_hibernation:1;
1000 unsigned sysdev_is_parent:1;
1001 unsigned has_lpm_erratum:1;
1002 unsigned is_utmi_l1_suspend:1;
1003 unsigned is_fpga:1;
1004 unsigned pending_events:1;
1005 unsigned pullups_connected:1;
1006 unsigned setup_packet_pending:1;
1007 unsigned three_stage_setup:1;
1008 unsigned usb3_lpm_capable:1;
1009
1010 unsigned disable_scramble_quirk:1;
1011 unsigned u2exit_lfps_quirk:1;
1012 unsigned u2ss_inp3_quirk:1;
1013 unsigned req_p1p2p3_quirk:1;
1014 unsigned del_p1p2p3_quirk:1;
1015 unsigned del_phy_power_chg_quirk:1;
1016 unsigned lfps_filter_quirk:1;
1017 unsigned rx_detect_poll_quirk:1;
1018 unsigned dis_u3_susphy_quirk:1;
1019 unsigned dis_u2_susphy_quirk:1;
1020 unsigned dis_enblslpm_quirk:1;
1021 unsigned dis_rxdet_inp3_quirk:1;
1022 unsigned dis_u2_freeclk_exists_quirk:1;
1023 unsigned dis_del_phy_power_chg_quirk:1;
1024 unsigned dis_tx_ipgap_linecheck_quirk:1;
1025
1026 unsigned tx_de_emphasis_quirk:1;
1027 unsigned tx_de_emphasis:2;
1028
1029 unsigned dis_metastability_quirk:1;
1030
1031 u16 imod_interval;
1032 };
1033
1034 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1035
1036 /* -------------------------------------------------------------------------- */
1037
1038 struct dwc3_event_type {
1039 u32 is_devspec:1;
1040 u32 type:7;
1041 u32 reserved8_31:24;
1042 } __packed;
1043
1044 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
1045 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
1046 #define DWC3_DEPEVT_XFERNOTREADY 0x03
1047 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1048 #define DWC3_DEPEVT_STREAMEVT 0x06
1049 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1050
1051 /**
1052 * struct dwc3_event_depvt - Device Endpoint Events
1053 * @one_bit: indicates this is an endpoint event (not used)
1054 * @endpoint_number: number of the endpoint
1055 * @endpoint_event: The event we have:
1056 * 0x00 - Reserved
1057 * 0x01 - XferComplete
1058 * 0x02 - XferInProgress
1059 * 0x03 - XferNotReady
1060 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1061 * 0x05 - Reserved
1062 * 0x06 - StreamEvt
1063 * 0x07 - EPCmdCmplt
1064 * @reserved11_10: Reserved, don't use.
1065 * @status: Indicates the status of the event. Refer to databook for
1066 * more information.
1067 * @parameters: Parameters of the current event. Refer to databook for
1068 * more information.
1069 */
1070 struct dwc3_event_depevt {
1071 u32 one_bit:1;
1072 u32 endpoint_number:5;
1073 u32 endpoint_event:4;
1074 u32 reserved11_10:2;
1075 u32 status:4;
1076
1077 /* Within XferNotReady */
1078 #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1079
1080 /* Within XferComplete */
1081 #define DEPEVT_STATUS_BUSERR BIT(0)
1082 #define DEPEVT_STATUS_SHORT BIT(1)
1083 #define DEPEVT_STATUS_IOC BIT(2)
1084 #define DEPEVT_STATUS_LST BIT(3)
1085
1086 /* Stream event only */
1087 #define DEPEVT_STREAMEVT_FOUND 1
1088 #define DEPEVT_STREAMEVT_NOTFOUND 2
1089
1090 /* Control-only Status */
1091 #define DEPEVT_STATUS_CONTROL_DATA 1
1092 #define DEPEVT_STATUS_CONTROL_STATUS 2
1093 #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1094
1095 /* In response to Start Transfer */
1096 #define DEPEVT_TRANSFER_NO_RESOURCE 1
1097 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
1098
1099 u32 parameters:16;
1100
1101 /* For Command Complete Events */
1102 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1103 } __packed;
1104
1105 /**
1106 * struct dwc3_event_devt - Device Events
1107 * @one_bit: indicates this is a non-endpoint event (not used)
1108 * @device_event: indicates it's a device event. Should read as 0x00
1109 * @type: indicates the type of device event.
1110 * 0 - DisconnEvt
1111 * 1 - USBRst
1112 * 2 - ConnectDone
1113 * 3 - ULStChng
1114 * 4 - WkUpEvt
1115 * 5 - Reserved
1116 * 6 - EOPF
1117 * 7 - SOF
1118 * 8 - Reserved
1119 * 9 - ErrticErr
1120 * 10 - CmdCmplt
1121 * 11 - EvntOverflow
1122 * 12 - VndrDevTstRcved
1123 * @reserved15_12: Reserved, not used
1124 * @event_info: Information about this event
1125 * @reserved31_25: Reserved, not used
1126 */
1127 struct dwc3_event_devt {
1128 u32 one_bit:1;
1129 u32 device_event:7;
1130 u32 type:4;
1131 u32 reserved15_12:4;
1132 u32 event_info:9;
1133 u32 reserved31_25:7;
1134 } __packed;
1135
1136 /**
1137 * struct dwc3_event_gevt - Other Core Events
1138 * @one_bit: indicates this is a non-endpoint event (not used)
1139 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1140 * @phy_port_number: self-explanatory
1141 * @reserved31_12: Reserved, not used.
1142 */
1143 struct dwc3_event_gevt {
1144 u32 one_bit:1;
1145 u32 device_event:7;
1146 u32 phy_port_number:4;
1147 u32 reserved31_12:20;
1148 } __packed;
1149
1150 /**
1151 * union dwc3_event - representation of Event Buffer contents
1152 * @raw: raw 32-bit event
1153 * @type: the type of the event
1154 * @depevt: Device Endpoint Event
1155 * @devt: Device Event
1156 * @gevt: Global Event
1157 */
1158 union dwc3_event {
1159 u32 raw;
1160 struct dwc3_event_type type;
1161 struct dwc3_event_depevt depevt;
1162 struct dwc3_event_devt devt;
1163 struct dwc3_event_gevt gevt;
1164 };
1165
1166 /**
1167 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1168 * parameters
1169 * @param2: third parameter
1170 * @param1: second parameter
1171 * @param0: first parameter
1172 */
1173 struct dwc3_gadget_ep_cmd_params {
1174 u32 param2;
1175 u32 param1;
1176 u32 param0;
1177 };
1178
1179 /*
1180 * DWC3 Features to be used as Driver Data
1181 */
1182
1183 #define DWC3_HAS_PERIPHERAL BIT(0)
1184 #define DWC3_HAS_XHCI BIT(1)
1185 #define DWC3_HAS_OTG BIT(3)
1186
1187 /* prototypes */
1188 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1189 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1190
1191 /* check whether we are on the DWC_usb3 core */
dwc3_is_usb3(struct dwc3 * dwc)1192 static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1193 {
1194 return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1195 }
1196
1197 /* check whether we are on the DWC_usb31 core */
dwc3_is_usb31(struct dwc3 * dwc)1198 static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1199 {
1200 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1201 }
1202
1203 bool dwc3_has_imod(struct dwc3 *dwc);
1204
1205 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1206 int dwc3_host_init(struct dwc3 *dwc);
1207 void dwc3_host_exit(struct dwc3 *dwc);
1208 #else
dwc3_host_init(struct dwc3 * dwc)1209 static inline int dwc3_host_init(struct dwc3 *dwc)
1210 { return 0; }
dwc3_host_exit(struct dwc3 * dwc)1211 static inline void dwc3_host_exit(struct dwc3 *dwc)
1212 { }
1213 #endif
1214
1215 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1216 int dwc3_gadget_init(struct dwc3 *dwc);
1217 void dwc3_gadget_exit(struct dwc3 *dwc);
1218 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1219 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1220 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1221 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1222 struct dwc3_gadget_ep_cmd_params *params);
1223 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1224 #else
dwc3_gadget_init(struct dwc3 * dwc)1225 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1226 { return 0; }
dwc3_gadget_exit(struct dwc3 * dwc)1227 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1228 { }
dwc3_gadget_set_test_mode(struct dwc3 * dwc,int mode)1229 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1230 { return 0; }
dwc3_gadget_get_link_state(struct dwc3 * dwc)1231 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1232 { return 0; }
dwc3_gadget_set_link_state(struct dwc3 * dwc,enum dwc3_link_state state)1233 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1234 enum dwc3_link_state state)
1235 { return 0; }
1236
dwc3_send_gadget_ep_cmd(struct dwc3_ep * dep,unsigned cmd,struct dwc3_gadget_ep_cmd_params * params)1237 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1238 struct dwc3_gadget_ep_cmd_params *params)
1239 { return 0; }
dwc3_send_gadget_generic_command(struct dwc3 * dwc,int cmd,u32 param)1240 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1241 int cmd, u32 param)
1242 { return 0; }
1243 #endif
1244
1245 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1246 int dwc3_drd_init(struct dwc3 *dwc);
1247 void dwc3_drd_exit(struct dwc3 *dwc);
1248 #else
dwc3_drd_init(struct dwc3 * dwc)1249 static inline int dwc3_drd_init(struct dwc3 *dwc)
1250 { return 0; }
dwc3_drd_exit(struct dwc3 * dwc)1251 static inline void dwc3_drd_exit(struct dwc3 *dwc)
1252 { }
1253 #endif
1254
1255 /* power management interface */
1256 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1257 int dwc3_gadget_suspend(struct dwc3 *dwc);
1258 int dwc3_gadget_resume(struct dwc3 *dwc);
1259 void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1260 #else
dwc3_gadget_suspend(struct dwc3 * dwc)1261 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1262 {
1263 return 0;
1264 }
1265
dwc3_gadget_resume(struct dwc3 * dwc)1266 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1267 {
1268 return 0;
1269 }
1270
dwc3_gadget_process_pending_events(struct dwc3 * dwc)1271 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1272 {
1273 }
1274 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1275
1276 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1277 int dwc3_ulpi_init(struct dwc3 *dwc);
1278 void dwc3_ulpi_exit(struct dwc3 *dwc);
1279 #else
dwc3_ulpi_init(struct dwc3 * dwc)1280 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1281 { return 0; }
dwc3_ulpi_exit(struct dwc3 * dwc)1282 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1283 { }
1284 #endif
1285
1286 #endif /* __DRIVERS_USB_DWC3_CORE_H */
1287