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Searched refs:EN0_ISR (Results 1 – 8 of 8) sorted by relevance

/drivers/net/ethernet/8390/
Dlib8390.c265 isr = ei_inb(e8390_base+EN0_ISR); in __ei_tx_timeout()
444 ei_inb_p(e8390_base + EN0_ISR), in __ei_interrupt()
453 ei_inb_p(e8390_base + EN0_ISR)); in __ei_interrupt()
456 while ((interrupts = ei_inb_p(e8390_base + EN0_ISR)) != 0 && in __ei_interrupt()
461 ei_outb_p(interrupts, e8390_base + EN0_ISR); in __ei_interrupt()
481 ei_outb_p(ENISR_COUNTERS, e8390_base + EN0_ISR); /* Ack intr. */ in __ei_interrupt()
486 ei_outb_p(ENISR_RDC, e8390_base + EN0_ISR); in __ei_interrupt()
498 ei_outb_p(ENISR_ALL, e8390_base + EN0_ISR); /* Ack. most intrs. */ in __ei_interrupt()
501 ei_outb_p(0xff, e8390_base + EN0_ISR); /* Ack. all intrs. */ in __ei_interrupt()
554 ei_outb_p(ENISR_TX_ERR, e8390_base + EN0_ISR); /* Ack intr. */ in ei_tx_err()
[all …]
Dne2k-pci.c297 while ((inb(ioaddr + EN0_ISR) & ENISR_RESET) == 0) in ne2k_pci_init_one()
305 outb(0xff, ioaddr + EN0_ISR); /* Ack all intr. */ in ne2k_pci_init_one()
319 {0xFF, EN0_ISR}, in ne2k_pci_init_one()
468 while ((inb(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) in ne2k_pci_reset_8390()
473 outb(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */ in ne2k_pci_reset_8390()
508 outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne2k_pci_get_8390_hdr()
560 outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne2k_pci_block_input()
600 outb(ENISR_RDC, nic_base + EN0_ISR); in ne2k_pci_block_output()
625 while ((inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) in ne2k_pci_block_output()
633 outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne2k_pci_block_output()
Daxnet_cs.c203 {0xFF, EN0_ISR}, in get_prom()
478 outb_p(0xFF, nic_base + EN0_ISR); /* Clear bogus intr. */ in axnet_open()
530 if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0) in axnet_reset_8390()
534 outb_p(ENISR_RESET, nic_base + EN0_ISR); /* Ack intr. */ in axnet_reset_8390()
562 if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) { in ei_watchdog()
918 isr = inb(e8390_base+EN0_ISR); in axnet_tx_timeout()
1114 inb_p(e8390_base + EN0_ISR), in ax_interrupt()
1122 inb_p(e8390_base + EN0_ISR)); in ax_interrupt()
1124 outb_p(0x00, e8390_base + EN0_ISR); in ax_interrupt()
1128 while ((interrupts = inb_p(e8390_base + EN0_ISR)) != 0 && in ax_interrupt()
[all …]
Dne.c352 while ((inb_p(ioaddr + EN0_ISR) & ENISR_RESET) == 0) in ne_probe1()
364 outb_p(0xff, ioaddr + EN0_ISR); /* Ack all intr. */ in ne_probe1()
379 {0xFF, EN0_ISR}, in ne_probe1()
580 while ((inb_p(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) in ne_reset_8390()
585 outb_p(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */ in ne_reset_8390()
619 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne_get_8390_hdr()
693 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne_block_input()
745 outb_p(ENISR_RDC, nic_base + EN0_ISR); in ne_block_output()
789 while ((inb_p(nic_base + EN0_ISR) & ENISR_RDC) == 0) in ne_block_output()
797 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne_block_output()
Dpcnet_cs.c335 {0xFF, EN0_ISR}, in get_prom()
911 outb_p(0xFF, nic_base + EN0_ISR); /* Clear bogus intr. */ in pcnet_open()
964 if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0) in pcnet_reset_8390()
968 outb_p(ENISR_RESET, nic_base + EN0_ISR); /* Ack intr. */ in pcnet_reset_8390()
1021 if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) { in ei_watchdog()
1148 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in dma_get_8390_hdr()
1203 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in dma_block_input()
1243 outb_p(ENISR_RDC, nic_base + EN0_ISR); in dma_block_output()
1279 while ((inb_p(nic_base + EN0_ISR) & ENISR_RDC) == 0) in dma_block_output()
1287 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in dma_block_output()
Detherh.c345 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_block_output()
359 while ((readb (addr + EN0_ISR) & ENISR_RDC) == 0) in etherh_block_output()
367 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_block_output()
408 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_block_input()
445 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_get_header()
Dax88796.c158 while ((ei_inb(addr + EN0_ISR) & ENISR_RESET) == 0) { in ax_reset_8390()
165 ei_outb(ENISR_RESET, addr + EN0_ISR); /* Ack intr. */ in ax_reset_8390()
199 ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ax_get_8390_hdr()
278 ei_outb(ENISR_RDC, nic_base + EN0_ISR); in ax_block_output()
294 while ((ei_inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) { in ax_block_output()
303 ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ax_block_output()
D8390.h167 #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ macro