Searched refs:GEN6_VERSYNC (Results 1 – 2 of 2) sorted by relevance
2051 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, in intel_ring_init_semaphores()
2307 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) macro