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Searched refs:GEN6_VERSYNC (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_ringbuffer.c2051 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, in intel_ring_init_semaphores()
Di915_reg.h2307 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) macro