Home
last modified time | relevance | path

Searched refs:IH_RB_WPTR (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsi_ih.c53 WREG32(IH_RB_WPTR, 0); in si_ih_disable_interrupts()
84 WREG32(IH_RB_WPTR, 0); in si_ih_irq_init()
Diceland_ih.c194 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in iceland_ih_get_wptr()
195 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in iceland_ih_get_wptr()
Dcz_ih.c194 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in cz_ih_get_wptr()
195 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in cz_ih_get_wptr()
Dtonga_ih.c205 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in tonga_ih_get_wptr()
206 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in tonga_ih_get_wptr()
Dvega10_ih.c210 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in vega10_ih_get_wptr()
211 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in vega10_ih_get_wptr()
Dsid.h665 #define IH_RB_WPTR 0xF83 macro
/drivers/gpu/drm/radeon/
Dr600.c3610 WREG32(IH_RB_WPTR, 0); in r600_disable_interrupts()
3722 WREG32(IH_RB_WPTR, 0); in r600_irq_init()
4041 wptr = RREG32(IH_RB_WPTR); in r600_get_ih_wptr()
4104 RREG32(IH_RB_WPTR); in r600_irq_process()
Dsid.h661 #define IH_RB_WPTR 0x3e0c macro
Dcikd.h813 #define IH_RB_WPTR 0x3e0c macro
Devergreend.h1230 #define IH_RB_WPTR 0x3e0c macro
Dsi.c5939 WREG32(IH_RB_WPTR, 0); in si_disable_interrupts()
6025 WREG32(IH_RB_WPTR, 0); in si_irq_init()
6213 wptr = RREG32(IH_RB_WPTR); in si_get_ih_wptr()
Dr600d.h669 #define IH_RB_WPTR 0x3e0c macro
Dcik.c6900 WREG32(IH_RB_WPTR, 0); in cik_disable_interrupts()
7044 WREG32(IH_RB_WPTR, 0); in cik_irq_init()
7477 wptr = RREG32(IH_RB_WPTR); in cik_get_ih_wptr()
Devergreen.c4678 wptr = RREG32(IH_RB_WPTR); in evergreen_get_ih_wptr()