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Searched refs:INVALIDATE_ALL_L1_TLBS (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c142 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_0_init_cache_regs()
Dmmhub_v1_0.c156 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs()
Dgmc_v7_0.c612 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable()
Dgmc_v8_0.c841 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
Dsid.h381 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
/drivers/gpu/drm/radeon/
Drv770d.h648 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
Dnid.h118 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
Dsid.h379 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
Dcikd.h499 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
Devergreend.h1156 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
Dr600d.h593 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
Dni.c1296 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
Dsi.c4307 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
Dcik.c5487 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()