Searched refs:KHZ (Results 1 – 9 of 9) sorted by relevance
22 #define KHZ 1000 macro23 #define MHZ (KHZ * KHZ)
122 #define KHZ 1000 macro123 #define MHZ (KHZ * KHZ)203 case 9600 * KHZ: in exynos5_rate_to_clk()212 case 19200 * KHZ: in exynos5_rate_to_clk()
140 case 9600 * KHZ: in exynos4x12_rate_to_clk()149 case 19200 * KHZ: in exynos4x12_rate_to_clk()
150 case 9600 * KHZ: in exynos5250_rate_to_clk()159 case 19200 * KHZ: in exynos5250_rate_to_clk()
27 #define KHZ (1000) macro28 #define MHZ (KHZ * 1000)146 clk->parent_rate / KHZ); in gk20a_pllg_n_lo()
113 target_clk_f = rate * 2 / KHZ; in gk20a_pllg_calc_mnp()114 ref_clk_f = clk->parent_rate / KHZ; in gk20a_pllg_calc_mnp()195 target_clk_f / KHZ); in gk20a_pllg_calc_mnp()205 target_freq / KHZ, pll->m, pll->n, pll->pl, in gk20a_pllg_calc_mnp()530 clk->parent_rate / KHZ); in gk20a_clk_setup_slide()636 clk->parent_rate / KHZ); in gk20a_clk_ctor()
490 u32 rate = gk20a_pllg_calc_rate(&clk->base, pll) / KHZ; in gm20b_dvfs_calc_safe_pll()491 u32 parent_rate = clk->base.parent_rate / KHZ; in gm20b_dvfs_calc_safe_pll()1049 (clk->base.parent_rate / KHZ)); in gm20b_clk_new()
80 #define KHZ 1000 macro221 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()396 tegra->cur_freq = data->new_rate / KHZ; in tegra_actmon_rate_notify_cb()510 stat->current_frequency = tegra->cur_freq * KHZ; in tegra_devfreq_get_dev_status()565 *freq = target_freq * KHZ; in tegra_governor_get_target()668 tegra->max_freq = clk_round_rate(tegra->emc_clock, ULONG_MAX) / KHZ; in tegra_devfreq_probe()669 tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ; in tegra_devfreq_probe()683 for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) { in tegra_devfreq_probe()
12 #define KHZ 1000 macro13 #define MHZ (KHZ * KHZ)