| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gk20a.h | 30 #define MASK(w) ((1 << (w)) - 1) macro
49 (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT)
59 (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT)
87 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
92 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
94 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
95 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
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| D | gm20b.c | 41 (MASK(GPCPLL_CFG2_SDM_DIN_WIDTH) << GPCPLL_CFG2_SDM_DIN_SHIFT)
45 (MASK(GPCPLL_CFG2_SDM_DIN_NEW_WIDTH) << GPCPLL_CFG2_SDM_DIN_NEW_SHIFT)
53 (MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH) << GPCPLL_DVFS0_DFS_COEFF_SHIFT)
57 (MASK(GPCPLL_DVFS0_DFS_DET_MAX_WIDTH) << GPCPLL_DVFS0_DFS_DET_MAX_SHIFT)
169 MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); in gm20b_pllg_read_mnp()
201 dvfs->dfs_coeff = min_t(u32, coeff, MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH)); in gm20b_dvfs_calc_det_coeff()
254 rem = ((u32)n) & MASK(DFS_DET_RANGE); in gm20b_dvfs_calc_ndiv()
259 *sdm_din = (rem >> BITS_PER_BYTE) & MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); in gm20b_dvfs_calc_ndiv()
536 nvkm_mask(device, GPC_BCAST_GPCPLL_DVFS2, MASK(DFS_DET_RANGE + 1), in gm20b_dvfs_program_ext_cal()
788 data &= MASK(GPCPLL_CFG3_PLL_DFS_TESTOUT_WIDTH); in gm20b_clk_init_dvfs()
[all …]
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| D | gk20a.c | 71 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
72 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
73 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
82 val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT; in gk20a_pllg_write_mnp()
83 val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; in gk20a_pllg_write_mnp()
84 val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT; in gk20a_pllg_write_mnp()
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| /drivers/scsi/sym53c8xx_2/ |
| D | sym_fw2.h | 241 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
329 SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)),
361 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
451 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
475 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
534 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
694 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
911 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
917 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1086 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
[all …]
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| D | sym_fw1.h | 249 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
376 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
466 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
491 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
551 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
717 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
962 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
968 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1200 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1220 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
[all …]
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| /drivers/gpu/drm/hisilicon/kirin/ |
| D | kirin_ade_reg.h | 17 #define MASK(x) (BIT(x) - 1) macro
21 #define FRM_END_START_MASK MASK(2)
54 #define CH_OVLY_SEL_MASK MASK(2)
103 #define QOSGENERATOR_MODE_MASK MASK(2)
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| D | kirin_drm_ade.c | 143 MASK(1), !!val); in ade_update_reload_bit()
169 writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); in ade_init()
170 writel(MASK(32), base + ADE_SOFT_RST_SEL(1)); in ade_init()
171 writel(MASK(32), base + ADE_RELOAD_DIS(0)); in ade_init()
172 writel(MASK(32), base + ADE_RELOAD_DIS(1)); in ade_init()
328 MASK(1), 1); in ade_crtc_enable_vblank()
345 MASK(1), 0); in ade_crtc_disable_vblank()
362 MASK(1), 1); in ade_irq_handler()
774 MASK(1), 0); in ade_compositor_routing_disable()
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| D | dw_drm_dsi.c | 349 dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time); in dsi_set_phy_timer()
350 dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time); in dsi_set_phy_timer()
351 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), in dsi_set_phy_timer()
353 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), in dsi_set_phy_timer()
355 dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8), in dsi_set_phy_timer()
357 dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8), in dsi_set_phy_timer()
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| D | dw_dsi_reg.h | 14 #define MASK(x) (BIT(x) - 1) macro
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| /drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 145 #define MASK(x) (BIT(x) - 1) macro
150 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
157 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
164 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
170 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
176 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
183 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
190 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
197 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
204 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
[all …]
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| /drivers/scsi/ |
| D | vmw_pvscsi.h | 33 #define MASK(n) ((1 << (n)) - 1) /* make an n-bit mask */ macro
412 #define PVSCSI_INTR_CMPL_MASK MASK(2)
416 #define PVSCSI_INTR_MSG_MASK (MASK(2) << 2)
418 #define PVSCSI_INTR_ALL_SUPPORTED MASK(4)
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| /drivers/dma/dw/ |
| D | core.c | 192 channel_set_bit(dw, MASK.XFER, dwc->mask); in dwc_initialize()
193 channel_set_bit(dw, MASK.ERROR, dwc->mask); in dwc_initialize()
590 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_tasklet()
591 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_tasklet()
614 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_interrupt()
615 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); in dw_dma_interrupt()
616 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_interrupt()
625 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); in dw_dma_interrupt()
626 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); in dw_dma_interrupt()
627 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); in dw_dma_interrupt()
[all …]
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| /drivers/gpu/drm/i915/ |
| D | i915_syncmap.c | 33 #define MASK (KSYNCMAP - 1) macro
114 return (id >> p->height) & MASK; in __sync_branch_idx()
121 return id & MASK; in __sync_leaf_idx()
305 idx = p->prefix >> (above - SHIFT) & MASK; in __sync_set()
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| /drivers/tty/ |
| D | n_tty.c | 129 #define MASK(x) ((x) & (N_TTY_BUF_SIZE - 1)) macro
636 while (MASK(ldata->echo_commit) != MASK(tail)) { in __process_echoes()
647 if (MASK(ldata->echo_commit) == MASK(tail + 1)) in __process_echoes()
660 if (MASK(ldata->echo_commit) == MASK(tail + 2)) in __process_echoes()
1013 while (MASK(ldata->read_head) != MASK(ldata->canon_head)) { in eraser()
1021 MASK(head) != MASK(ldata->canon_head)); in eraser()
1063 while (MASK(tail) != MASK(ldata->canon_head)) { in eraser()
1338 while (MASK(tail) != MASK(ldata->read_head)) { in n_tty_receive_char_special()
2439 while (MASK(head) != MASK(tail)) { in inq_canon()
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| /drivers/dma/ |
| D | idma64.c | 45 channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask); in idma64_off()
46 channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask); in idma64_off()
47 channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask); in idma64_off()
48 channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask); in idma64_off()
49 channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask); in idma64_off()
75 channel_set_bit(idma64, MASK(XFER), idma64c->mask); in idma64_chan_init()
76 channel_set_bit(idma64, MASK(ERROR), idma64c->mask); in idma64_chan_init()
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| /drivers/staging/xgifb/ |
| D | vb_struct.h | 58 unsigned short MASK; member
64 unsigned short MASK; member
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | cursor.c | 47 MASK(NV_CIO_CRE_HCUR_ASI) | in nv04_cursor_set_offset()
53 MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); in nv04_cursor_set_offset()
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| D | hw.h | 32 #define MASK(field) ( \ macro
36 (((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield))
380 *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); in nv_show_cursor()
382 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); in nv_show_cursor()
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| /drivers/scsi/aic7xxx/aicasm/ |
| D | aicasm_symbol.c | 105 case MASK: in symbol_delete()
247 case MASK: in symlist_add()
505 case MASK: in symtable_dump()
632 case MASK: in symtable_dump()
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| D | aicasm_symbol.h | 59 MASK, enumerator
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| D | aicasm_gram.y | 532 process_field(MASK, $2, $3.value);
711 case MASK:
1440 if (field_type != MASK && value == 0) {
1514 case MASK: in initialize_symbol()
1899 if ((node->symbol->type == MASK in type_check()
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| /drivers/char/xilinx_hwicap/ |
| D | xilinx_hwicap.c | 127 .MASK = 6,
152 .MASK = 6,
177 .MASK = 6,
202 .MASK = 6,
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| D | xilinx_hwicap.h | 131 u32 MASK; member
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| /drivers/platform/x86/ |
| D | compal-laptop.c | 382 #define SIMPLE_MASKED_STORE_SHOW(NAME, ADDR, MASK) \ argument
386 return sprintf(buf, "%d\n", ((ec_read_u8(ADDR) & MASK) != 0)); \
395 ec_write(ADDR, state ? (old_val | MASK) : (old_val & ~MASK)); \
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| /drivers/gpu/drm/omapdrm/ |
| D | omap_dmm_tiler.h | 74 #define MASK(bits) ((1 << (bits)) - 1) macro
|