1 /*
2 * A devfreq driver for NVIDIA Tegra SoCs
3 *
4 * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved.
5 * Copyright (C) 2014 Google, Inc
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 *
19 */
20
21 #include <linux/clk.h>
22 #include <linux/cpufreq.h>
23 #include <linux/devfreq.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_opp.h>
29 #include <linux/reset.h>
30
31 #include "governor.h"
32
33 #define ACTMON_GLB_STATUS 0x0
34 #define ACTMON_GLB_PERIOD_CTRL 0x4
35
36 #define ACTMON_DEV_CTRL 0x0
37 #define ACTMON_DEV_CTRL_K_VAL_SHIFT 10
38 #define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18)
39 #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN BIT(20)
40 #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN BIT(21)
41 #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT 23
42 #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT 26
43 #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN BIT(29)
44 #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN BIT(30)
45 #define ACTMON_DEV_CTRL_ENB BIT(31)
46
47 #define ACTMON_DEV_UPPER_WMARK 0x4
48 #define ACTMON_DEV_LOWER_WMARK 0x8
49 #define ACTMON_DEV_INIT_AVG 0xc
50 #define ACTMON_DEV_AVG_UPPER_WMARK 0x10
51 #define ACTMON_DEV_AVG_LOWER_WMARK 0x14
52 #define ACTMON_DEV_COUNT_WEIGHT 0x18
53 #define ACTMON_DEV_AVG_COUNT 0x20
54 #define ACTMON_DEV_INTR_STATUS 0x24
55
56 #define ACTMON_INTR_STATUS_CLEAR 0xffffffff
57
58 #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER BIT(31)
59 #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER BIT(30)
60
61 #define ACTMON_ABOVE_WMARK_WINDOW 1
62 #define ACTMON_BELOW_WMARK_WINDOW 3
63 #define ACTMON_BOOST_FREQ_STEP 16000
64
65 /*
66 * Activity counter is incremented every 256 memory transactions, and each
67 * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is
68 * 4 * 256 = 1024.
69 */
70 #define ACTMON_COUNT_WEIGHT 0x400
71
72 /*
73 * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which
74 * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128
75 */
76 #define ACTMON_AVERAGE_WINDOW_LOG2 6
77 #define ACTMON_SAMPLING_PERIOD 12 /* ms */
78 #define ACTMON_DEFAULT_AVG_BAND 6 /* 1/10 of % */
79
80 #define KHZ 1000
81
82 /* Assume that the bus is saturated if the utilization is 25% */
83 #define BUS_SATURATION_RATIO 25
84
85 /**
86 * struct tegra_devfreq_device_config - configuration specific to an ACTMON
87 * device
88 *
89 * Coefficients and thresholds are percentages unless otherwise noted
90 */
91 struct tegra_devfreq_device_config {
92 u32 offset;
93 u32 irq_mask;
94
95 /* Factors applied to boost_freq every consecutive watermark breach */
96 unsigned int boost_up_coeff;
97 unsigned int boost_down_coeff;
98
99 /* Define the watermark bounds when applied to the current avg */
100 unsigned int boost_up_threshold;
101 unsigned int boost_down_threshold;
102
103 /*
104 * Threshold of activity (cycles) below which the CPU frequency isn't
105 * to be taken into account. This is to avoid increasing the EMC
106 * frequency when the CPU is very busy but not accessing the bus often.
107 */
108 u32 avg_dependency_threshold;
109 };
110
111 enum tegra_actmon_device {
112 MCALL = 0,
113 MCCPU,
114 };
115
116 static struct tegra_devfreq_device_config actmon_device_configs[] = {
117 {
118 /* MCALL: All memory accesses (including from the CPUs) */
119 .offset = 0x1c0,
120 .irq_mask = 1 << 26,
121 .boost_up_coeff = 200,
122 .boost_down_coeff = 50,
123 .boost_up_threshold = 60,
124 .boost_down_threshold = 40,
125 },
126 {
127 /* MCCPU: memory accesses from the CPUs */
128 .offset = 0x200,
129 .irq_mask = 1 << 25,
130 .boost_up_coeff = 800,
131 .boost_down_coeff = 90,
132 .boost_up_threshold = 27,
133 .boost_down_threshold = 10,
134 .avg_dependency_threshold = 50000,
135 },
136 };
137
138 /**
139 * struct tegra_devfreq_device - state specific to an ACTMON device
140 *
141 * Frequencies are in kHz.
142 */
143 struct tegra_devfreq_device {
144 const struct tegra_devfreq_device_config *config;
145 void __iomem *regs;
146 spinlock_t lock;
147
148 /* Average event count sampled in the last interrupt */
149 u32 avg_count;
150
151 /*
152 * Extra frequency to increase the target by due to consecutive
153 * watermark breaches.
154 */
155 unsigned long boost_freq;
156
157 /* Optimal frequency calculated from the stats for this device */
158 unsigned long target_freq;
159 };
160
161 struct tegra_devfreq {
162 struct devfreq *devfreq;
163
164 struct reset_control *reset;
165 struct clk *clock;
166 void __iomem *regs;
167
168 struct clk *emc_clock;
169 unsigned long max_freq;
170 unsigned long cur_freq;
171 struct notifier_block rate_change_nb;
172
173 struct tegra_devfreq_device devices[ARRAY_SIZE(actmon_device_configs)];
174 };
175
176 struct tegra_actmon_emc_ratio {
177 unsigned long cpu_freq;
178 unsigned long emc_freq;
179 };
180
181 static struct tegra_actmon_emc_ratio actmon_emc_ratios[] = {
182 { 1400000, ULONG_MAX },
183 { 1200000, 750000 },
184 { 1100000, 600000 },
185 { 1000000, 500000 },
186 { 800000, 375000 },
187 { 500000, 200000 },
188 { 250000, 100000 },
189 };
190
actmon_readl(struct tegra_devfreq * tegra,u32 offset)191 static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset)
192 {
193 return readl(tegra->regs + offset);
194 }
195
actmon_writel(struct tegra_devfreq * tegra,u32 val,u32 offset)196 static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset)
197 {
198 writel(val, tegra->regs + offset);
199 }
200
device_readl(struct tegra_devfreq_device * dev,u32 offset)201 static u32 device_readl(struct tegra_devfreq_device *dev, u32 offset)
202 {
203 return readl(dev->regs + offset);
204 }
205
device_writel(struct tegra_devfreq_device * dev,u32 val,u32 offset)206 static void device_writel(struct tegra_devfreq_device *dev, u32 val,
207 u32 offset)
208 {
209 writel(val, dev->regs + offset);
210 }
211
do_percent(unsigned long val,unsigned int pct)212 static unsigned long do_percent(unsigned long val, unsigned int pct)
213 {
214 return val * pct / 100;
215 }
216
tegra_devfreq_update_avg_wmark(struct tegra_devfreq * tegra,struct tegra_devfreq_device * dev)217 static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra,
218 struct tegra_devfreq_device *dev)
219 {
220 u32 avg = dev->avg_count;
221 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ;
222 u32 band = avg_band_freq * ACTMON_SAMPLING_PERIOD;
223
224 device_writel(dev, avg + band, ACTMON_DEV_AVG_UPPER_WMARK);
225
226 avg = max(dev->avg_count, band);
227 device_writel(dev, avg - band, ACTMON_DEV_AVG_LOWER_WMARK);
228 }
229
tegra_devfreq_update_wmark(struct tegra_devfreq * tegra,struct tegra_devfreq_device * dev)230 static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra,
231 struct tegra_devfreq_device *dev)
232 {
233 u32 val = tegra->cur_freq * ACTMON_SAMPLING_PERIOD;
234
235 device_writel(dev, do_percent(val, dev->config->boost_up_threshold),
236 ACTMON_DEV_UPPER_WMARK);
237
238 device_writel(dev, do_percent(val, dev->config->boost_down_threshold),
239 ACTMON_DEV_LOWER_WMARK);
240 }
241
actmon_write_barrier(struct tegra_devfreq * tegra)242 static void actmon_write_barrier(struct tegra_devfreq *tegra)
243 {
244 /* ensure the update has reached the ACTMON */
245 wmb();
246 actmon_readl(tegra, ACTMON_GLB_STATUS);
247 }
248
actmon_isr_device(struct tegra_devfreq * tegra,struct tegra_devfreq_device * dev)249 static void actmon_isr_device(struct tegra_devfreq *tegra,
250 struct tegra_devfreq_device *dev)
251 {
252 unsigned long flags;
253 u32 intr_status, dev_ctrl;
254
255 spin_lock_irqsave(&dev->lock, flags);
256
257 dev->avg_count = device_readl(dev, ACTMON_DEV_AVG_COUNT);
258 tegra_devfreq_update_avg_wmark(tegra, dev);
259
260 intr_status = device_readl(dev, ACTMON_DEV_INTR_STATUS);
261 dev_ctrl = device_readl(dev, ACTMON_DEV_CTRL);
262
263 if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_UPPER) {
264 /*
265 * new_boost = min(old_boost * up_coef + step, max_freq)
266 */
267 dev->boost_freq = do_percent(dev->boost_freq,
268 dev->config->boost_up_coeff);
269 dev->boost_freq += ACTMON_BOOST_FREQ_STEP;
270
271 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
272
273 if (dev->boost_freq >= tegra->max_freq)
274 dev->boost_freq = tegra->max_freq;
275 else
276 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
277 } else if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_LOWER) {
278 /*
279 * new_boost = old_boost * down_coef
280 * or 0 if (old_boost * down_coef < step / 2)
281 */
282 dev->boost_freq = do_percent(dev->boost_freq,
283 dev->config->boost_down_coeff);
284
285 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
286
287 if (dev->boost_freq < (ACTMON_BOOST_FREQ_STEP >> 1))
288 dev->boost_freq = 0;
289 else
290 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
291 }
292
293 if (dev->config->avg_dependency_threshold) {
294 if (dev->avg_count >= dev->config->avg_dependency_threshold)
295 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
296 else if (dev->boost_freq == 0)
297 dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
298 }
299
300 device_writel(dev, dev_ctrl, ACTMON_DEV_CTRL);
301
302 device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
303
304 actmon_write_barrier(tegra);
305
306 spin_unlock_irqrestore(&dev->lock, flags);
307 }
308
actmon_isr(int irq,void * data)309 static irqreturn_t actmon_isr(int irq, void *data)
310 {
311 struct tegra_devfreq *tegra = data;
312 bool handled = false;
313 unsigned int i;
314 u32 val;
315
316 val = actmon_readl(tegra, ACTMON_GLB_STATUS);
317 for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
318 if (val & tegra->devices[i].config->irq_mask) {
319 actmon_isr_device(tegra, tegra->devices + i);
320 handled = true;
321 }
322 }
323
324 return handled ? IRQ_WAKE_THREAD : IRQ_NONE;
325 }
326
actmon_cpu_to_emc_rate(struct tegra_devfreq * tegra,unsigned long cpu_freq)327 static unsigned long actmon_cpu_to_emc_rate(struct tegra_devfreq *tegra,
328 unsigned long cpu_freq)
329 {
330 unsigned int i;
331 struct tegra_actmon_emc_ratio *ratio = actmon_emc_ratios;
332
333 for (i = 0; i < ARRAY_SIZE(actmon_emc_ratios); i++, ratio++) {
334 if (cpu_freq >= ratio->cpu_freq) {
335 if (ratio->emc_freq >= tegra->max_freq)
336 return tegra->max_freq;
337 else
338 return ratio->emc_freq;
339 }
340 }
341
342 return 0;
343 }
344
actmon_update_target(struct tegra_devfreq * tegra,struct tegra_devfreq_device * dev)345 static void actmon_update_target(struct tegra_devfreq *tegra,
346 struct tegra_devfreq_device *dev)
347 {
348 unsigned long cpu_freq = 0;
349 unsigned long static_cpu_emc_freq = 0;
350 unsigned int avg_sustain_coef;
351 unsigned long flags;
352
353 if (dev->config->avg_dependency_threshold) {
354 cpu_freq = cpufreq_get(0);
355 static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq);
356 }
357
358 spin_lock_irqsave(&dev->lock, flags);
359
360 dev->target_freq = dev->avg_count / ACTMON_SAMPLING_PERIOD;
361 avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold;
362 dev->target_freq = do_percent(dev->target_freq, avg_sustain_coef);
363 dev->target_freq += dev->boost_freq;
364
365 if (dev->avg_count >= dev->config->avg_dependency_threshold)
366 dev->target_freq = max(dev->target_freq, static_cpu_emc_freq);
367
368 spin_unlock_irqrestore(&dev->lock, flags);
369 }
370
actmon_thread_isr(int irq,void * data)371 static irqreturn_t actmon_thread_isr(int irq, void *data)
372 {
373 struct tegra_devfreq *tegra = data;
374
375 mutex_lock(&tegra->devfreq->lock);
376 update_devfreq(tegra->devfreq);
377 mutex_unlock(&tegra->devfreq->lock);
378
379 return IRQ_HANDLED;
380 }
381
tegra_actmon_rate_notify_cb(struct notifier_block * nb,unsigned long action,void * ptr)382 static int tegra_actmon_rate_notify_cb(struct notifier_block *nb,
383 unsigned long action, void *ptr)
384 {
385 struct clk_notifier_data *data = ptr;
386 struct tegra_devfreq *tegra;
387 struct tegra_devfreq_device *dev;
388 unsigned int i;
389 unsigned long flags;
390
391 if (action != POST_RATE_CHANGE)
392 return NOTIFY_OK;
393
394 tegra = container_of(nb, struct tegra_devfreq, rate_change_nb);
395
396 tegra->cur_freq = data->new_rate / KHZ;
397
398 for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
399 dev = &tegra->devices[i];
400
401 spin_lock_irqsave(&dev->lock, flags);
402 tegra_devfreq_update_wmark(tegra, dev);
403 spin_unlock_irqrestore(&dev->lock, flags);
404 }
405
406 actmon_write_barrier(tegra);
407
408 return NOTIFY_OK;
409 }
410
tegra_actmon_enable_interrupts(struct tegra_devfreq * tegra)411 static void tegra_actmon_enable_interrupts(struct tegra_devfreq *tegra)
412 {
413 struct tegra_devfreq_device *dev;
414 u32 val;
415 unsigned int i;
416
417 for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
418 dev = &tegra->devices[i];
419
420 val = device_readl(dev, ACTMON_DEV_CTRL);
421 val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN;
422 val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN;
423 val |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
424 val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
425
426 device_writel(dev, val, ACTMON_DEV_CTRL);
427 }
428
429 actmon_write_barrier(tegra);
430 }
431
tegra_actmon_disable_interrupts(struct tegra_devfreq * tegra)432 static void tegra_actmon_disable_interrupts(struct tegra_devfreq *tegra)
433 {
434 struct tegra_devfreq_device *dev;
435 u32 val;
436 unsigned int i;
437
438 for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
439 dev = &tegra->devices[i];
440
441 val = device_readl(dev, ACTMON_DEV_CTRL);
442 val &= ~ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN;
443 val &= ~ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN;
444 val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
445 val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
446
447 device_writel(dev, val, ACTMON_DEV_CTRL);
448 }
449
450 actmon_write_barrier(tegra);
451 }
452
tegra_actmon_configure_device(struct tegra_devfreq * tegra,struct tegra_devfreq_device * dev)453 static void tegra_actmon_configure_device(struct tegra_devfreq *tegra,
454 struct tegra_devfreq_device *dev)
455 {
456 u32 val = 0;
457
458 dev->target_freq = tegra->cur_freq;
459
460 dev->avg_count = tegra->cur_freq * ACTMON_SAMPLING_PERIOD;
461 device_writel(dev, dev->avg_count, ACTMON_DEV_INIT_AVG);
462
463 tegra_devfreq_update_avg_wmark(tegra, dev);
464 tegra_devfreq_update_wmark(tegra, dev);
465
466 device_writel(dev, ACTMON_COUNT_WEIGHT, ACTMON_DEV_COUNT_WEIGHT);
467 device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
468
469 val |= ACTMON_DEV_CTRL_ENB_PERIODIC;
470 val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1)
471 << ACTMON_DEV_CTRL_K_VAL_SHIFT;
472 val |= (ACTMON_BELOW_WMARK_WINDOW - 1)
473 << ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT;
474 val |= (ACTMON_ABOVE_WMARK_WINDOW - 1)
475 << ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT;
476 val |= ACTMON_DEV_CTRL_ENB;
477
478 device_writel(dev, val, ACTMON_DEV_CTRL);
479
480 actmon_write_barrier(tegra);
481 }
482
tegra_devfreq_target(struct device * dev,unsigned long * freq,u32 flags)483 static int tegra_devfreq_target(struct device *dev, unsigned long *freq,
484 u32 flags)
485 {
486 struct tegra_devfreq *tegra = dev_get_drvdata(dev);
487 struct dev_pm_opp *opp;
488 unsigned long rate;
489
490 opp = devfreq_recommended_opp(dev, freq, flags);
491 if (IS_ERR(opp)) {
492 dev_err(dev, "Failed to find opp for %lu Hz\n", *freq);
493 return PTR_ERR(opp);
494 }
495 rate = dev_pm_opp_get_freq(opp);
496 dev_pm_opp_put(opp);
497
498 clk_set_min_rate(tegra->emc_clock, rate);
499 clk_set_rate(tegra->emc_clock, 0);
500
501 return 0;
502 }
503
tegra_devfreq_get_dev_status(struct device * dev,struct devfreq_dev_status * stat)504 static int tegra_devfreq_get_dev_status(struct device *dev,
505 struct devfreq_dev_status *stat)
506 {
507 struct tegra_devfreq *tegra = dev_get_drvdata(dev);
508 struct tegra_devfreq_device *actmon_dev;
509
510 stat->current_frequency = tegra->cur_freq * KHZ;
511
512 /* To be used by the tegra governor */
513 stat->private_data = tegra;
514
515 /* The below are to be used by the other governors */
516
517 actmon_dev = &tegra->devices[MCALL];
518
519 /* Number of cycles spent on memory access */
520 stat->busy_time = device_readl(actmon_dev, ACTMON_DEV_AVG_COUNT);
521
522 /* The bus can be considered to be saturated way before 100% */
523 stat->busy_time *= 100 / BUS_SATURATION_RATIO;
524
525 /* Number of cycles in a sampling period */
526 stat->total_time = ACTMON_SAMPLING_PERIOD * tegra->cur_freq;
527
528 stat->busy_time = min(stat->busy_time, stat->total_time);
529
530 return 0;
531 }
532
533 static struct devfreq_dev_profile tegra_devfreq_profile = {
534 .polling_ms = 0,
535 .target = tegra_devfreq_target,
536 .get_dev_status = tegra_devfreq_get_dev_status,
537 };
538
tegra_governor_get_target(struct devfreq * devfreq,unsigned long * freq)539 static int tegra_governor_get_target(struct devfreq *devfreq,
540 unsigned long *freq)
541 {
542 struct devfreq_dev_status *stat;
543 struct tegra_devfreq *tegra;
544 struct tegra_devfreq_device *dev;
545 unsigned long target_freq = 0;
546 unsigned int i;
547 int err;
548
549 err = devfreq_update_stats(devfreq);
550 if (err)
551 return err;
552
553 stat = &devfreq->last_status;
554
555 tegra = stat->private_data;
556
557 for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
558 dev = &tegra->devices[i];
559
560 actmon_update_target(tegra, dev);
561
562 target_freq = max(target_freq, dev->target_freq);
563 }
564
565 *freq = target_freq * KHZ;
566
567 return 0;
568 }
569
tegra_governor_event_handler(struct devfreq * devfreq,unsigned int event,void * data)570 static int tegra_governor_event_handler(struct devfreq *devfreq,
571 unsigned int event, void *data)
572 {
573 struct tegra_devfreq *tegra;
574 int ret = 0;
575
576 tegra = dev_get_drvdata(devfreq->dev.parent);
577
578 switch (event) {
579 case DEVFREQ_GOV_START:
580 devfreq_monitor_start(devfreq);
581 tegra_actmon_enable_interrupts(tegra);
582 break;
583
584 case DEVFREQ_GOV_STOP:
585 tegra_actmon_disable_interrupts(tegra);
586 devfreq_monitor_stop(devfreq);
587 break;
588
589 case DEVFREQ_GOV_SUSPEND:
590 tegra_actmon_disable_interrupts(tegra);
591 devfreq_monitor_suspend(devfreq);
592 break;
593
594 case DEVFREQ_GOV_RESUME:
595 devfreq_monitor_resume(devfreq);
596 tegra_actmon_enable_interrupts(tegra);
597 break;
598 }
599
600 return ret;
601 }
602
603 static struct devfreq_governor tegra_devfreq_governor = {
604 .name = "tegra_actmon",
605 .get_target_freq = tegra_governor_get_target,
606 .event_handler = tegra_governor_event_handler,
607 };
608
tegra_devfreq_probe(struct platform_device * pdev)609 static int tegra_devfreq_probe(struct platform_device *pdev)
610 {
611 struct tegra_devfreq *tegra;
612 struct tegra_devfreq_device *dev;
613 struct resource *res;
614 unsigned int i;
615 unsigned long rate;
616 int irq;
617 int err;
618
619 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
620 if (!tegra)
621 return -ENOMEM;
622
623 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
624
625 tegra->regs = devm_ioremap_resource(&pdev->dev, res);
626 if (IS_ERR(tegra->regs))
627 return PTR_ERR(tegra->regs);
628
629 tegra->reset = devm_reset_control_get(&pdev->dev, "actmon");
630 if (IS_ERR(tegra->reset)) {
631 dev_err(&pdev->dev, "Failed to get reset\n");
632 return PTR_ERR(tegra->reset);
633 }
634
635 tegra->clock = devm_clk_get(&pdev->dev, "actmon");
636 if (IS_ERR(tegra->clock)) {
637 dev_err(&pdev->dev, "Failed to get actmon clock\n");
638 return PTR_ERR(tegra->clock);
639 }
640
641 tegra->emc_clock = devm_clk_get(&pdev->dev, "emc");
642 if (IS_ERR(tegra->emc_clock)) {
643 dev_err(&pdev->dev, "Failed to get emc clock\n");
644 return PTR_ERR(tegra->emc_clock);
645 }
646
647 clk_set_rate(tegra->emc_clock, ULONG_MAX);
648
649 tegra->rate_change_nb.notifier_call = tegra_actmon_rate_notify_cb;
650 err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb);
651 if (err) {
652 dev_err(&pdev->dev,
653 "Failed to register rate change notifier\n");
654 return err;
655 }
656
657 reset_control_assert(tegra->reset);
658
659 err = clk_prepare_enable(tegra->clock);
660 if (err) {
661 dev_err(&pdev->dev,
662 "Failed to prepare and enable ACTMON clock\n");
663 return err;
664 }
665
666 reset_control_deassert(tegra->reset);
667
668 tegra->max_freq = clk_round_rate(tegra->emc_clock, ULONG_MAX) / KHZ;
669 tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ;
670
671 actmon_writel(tegra, ACTMON_SAMPLING_PERIOD - 1,
672 ACTMON_GLB_PERIOD_CTRL);
673
674 for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) {
675 dev = tegra->devices + i;
676 dev->config = actmon_device_configs + i;
677 dev->regs = tegra->regs + dev->config->offset;
678 spin_lock_init(&dev->lock);
679
680 tegra_actmon_configure_device(tegra, dev);
681 }
682
683 for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) {
684 rate = clk_round_rate(tegra->emc_clock, rate);
685 dev_pm_opp_add(&pdev->dev, rate, 0);
686 }
687
688 irq = platform_get_irq(pdev, 0);
689 if (irq < 0) {
690 dev_err(&pdev->dev, "Failed to get IRQ: %d\n", irq);
691 return irq;
692 }
693
694 platform_set_drvdata(pdev, tegra);
695
696 err = devm_request_threaded_irq(&pdev->dev, irq, actmon_isr,
697 actmon_thread_isr, IRQF_SHARED,
698 "tegra-devfreq", tegra);
699 if (err) {
700 dev_err(&pdev->dev, "Interrupt request failed\n");
701 return err;
702 }
703
704 tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock);
705 tegra->devfreq = devm_devfreq_add_device(&pdev->dev,
706 &tegra_devfreq_profile,
707 "tegra_actmon",
708 NULL);
709
710 return 0;
711 }
712
tegra_devfreq_remove(struct platform_device * pdev)713 static int tegra_devfreq_remove(struct platform_device *pdev)
714 {
715 struct tegra_devfreq *tegra = platform_get_drvdata(pdev);
716 int irq = platform_get_irq(pdev, 0);
717 u32 val;
718 unsigned int i;
719
720 for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) {
721 val = device_readl(&tegra->devices[i], ACTMON_DEV_CTRL);
722 val &= ~ACTMON_DEV_CTRL_ENB;
723 device_writel(&tegra->devices[i], val, ACTMON_DEV_CTRL);
724 }
725
726 actmon_write_barrier(tegra);
727
728 devm_free_irq(&pdev->dev, irq, tegra);
729
730 clk_notifier_unregister(tegra->emc_clock, &tegra->rate_change_nb);
731
732 clk_disable_unprepare(tegra->clock);
733
734 return 0;
735 }
736
737 static const struct of_device_id tegra_devfreq_of_match[] = {
738 { .compatible = "nvidia,tegra124-actmon" },
739 { },
740 };
741
742 MODULE_DEVICE_TABLE(of, tegra_devfreq_of_match);
743
744 static struct platform_driver tegra_devfreq_driver = {
745 .probe = tegra_devfreq_probe,
746 .remove = tegra_devfreq_remove,
747 .driver = {
748 .name = "tegra-devfreq",
749 .of_match_table = tegra_devfreq_of_match,
750 },
751 };
752
tegra_devfreq_init(void)753 static int __init tegra_devfreq_init(void)
754 {
755 int ret = 0;
756
757 ret = devfreq_add_governor(&tegra_devfreq_governor);
758 if (ret) {
759 pr_err("%s: failed to add governor: %d\n", __func__, ret);
760 return ret;
761 }
762
763 ret = platform_driver_register(&tegra_devfreq_driver);
764 if (ret)
765 devfreq_remove_governor(&tegra_devfreq_governor);
766
767 return ret;
768 }
module_init(tegra_devfreq_init)769 module_init(tegra_devfreq_init)
770
771 static void __exit tegra_devfreq_exit(void)
772 {
773 int ret = 0;
774
775 platform_driver_unregister(&tegra_devfreq_driver);
776
777 ret = devfreq_remove_governor(&tegra_devfreq_governor);
778 if (ret)
779 pr_err("%s: failed to remove governor: %d\n", __func__, ret);
780 }
781 module_exit(tegra_devfreq_exit)
782
783 MODULE_LICENSE("GPL v2");
784 MODULE_DESCRIPTION("Tegra devfreq driver");
785 MODULE_AUTHOR("Tomeu Vizoso <tomeu.vizoso@collabora.com>");
786