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Searched refs:MC_SEQ_WR_CTL_D0 (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/radeon/
Dbtcd.h111 #define MC_SEQ_WR_CTL_D0 0x28bc macro
Dbtc_dpm.c1877 case MC_SEQ_WR_CTL_D0 >> 2: in btc_check_s0_mc_reg_index()
2035 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in btc_initialize_mc_reg_table()
Dnid.h787 #define MC_SEQ_WR_CTL_D0 0x28bc macro
Dsid.h548 #define MC_SEQ_WR_CTL_D0 0x28bc macro
Dcikd.h663 #define MC_SEQ_WR_CTL_D0 0x28bc macro
Devergreend.h293 #define MC_SEQ_WR_CTL_D0 0x28bc macro
Dci_dpm.c4424 case MC_SEQ_WR_CTL_D0 >> 2: in ci_check_s0_mc_reg_index()
4536 case MC_SEQ_WR_CTL_D0: in ci_register_patching_mc_seq()
4625 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in ci_initialize_mc_reg_table()
Dni_dpm.c2789 case MC_SEQ_WR_CTL_D0 >> 2: in ni_check_s0_mc_reg_index()
2888 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in ni_initialize_mc_reg_table()
Dcypress_dpm.c996 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2; in cypress_set_mc_reg_address_table()
Dsi_dpm.c5447 case MC_SEQ_WR_CTL_D0 >> 2: in si_check_s0_mc_reg_index()
5550 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in si_initialize_mc_reg_table()
/drivers/gpu/drm/amd/amdgpu/
Dsid.h550 #define MC_SEQ_WR_CTL_D0 0xA2F macro
Dsi_dpm.c5904 case MC_SEQ_WR_CTL_D0: in si_check_s0_mc_reg_index()
6007 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in si_initialize_mc_reg_table()