1 /**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18 /*! \file octeon_device.h
19 * \brief Host Driver: This file defines the octeon device structure.
20 */
21
22 #ifndef _OCTEON_DEVICE_H_
23 #define _OCTEON_DEVICE_H_
24
25 #include <linux/interrupt.h>
26
27 /** PCI VendorId Device Id */
28 #define OCTEON_CN68XX_PCIID 0x91177d
29 #define OCTEON_CN66XX_PCIID 0x92177d
30 #define OCTEON_CN23XX_PCIID_PF 0x9702177d
31 /** Driver identifies chips by these Ids, created by clubbing together
32 * DeviceId+RevisionId; Where Revision Id is not used to distinguish
33 * between chips, a value of 0 is used for revision id.
34 */
35 #define OCTEON_CN68XX 0x0091
36 #define OCTEON_CN66XX 0x0092
37 #define OCTEON_CN23XX_PF_VID 0x9702
38 #define OCTEON_CN23XX_VF_VID 0x9712
39
40 /**RevisionId for the chips */
41 #define OCTEON_CN23XX_REV_1_0 0x00
42 #define OCTEON_CN23XX_REV_1_1 0x01
43 #define OCTEON_CN23XX_REV_2_0 0x80
44
45 /** Endian-swap modes supported by Octeon. */
46 enum octeon_pci_swap_mode {
47 OCTEON_PCI_PASSTHROUGH = 0,
48 OCTEON_PCI_64BIT_SWAP = 1,
49 OCTEON_PCI_32BIT_BYTE_SWAP = 2,
50 OCTEON_PCI_32BIT_LW_SWAP = 3
51 };
52
53 enum {
54 OCTEON_CONFIG_TYPE_DEFAULT = 0,
55 NUM_OCTEON_CONFS,
56 };
57
58 #define OCTEON_INPUT_INTR (1)
59 #define OCTEON_OUTPUT_INTR (2)
60 #define OCTEON_MBOX_INTR (4)
61 #define OCTEON_ALL_INTR 0xff
62
63 /*--------------- PCI BAR1 index registers -------------*/
64
65 /* BAR1 Mask */
66 #define PCI_BAR1_ENABLE_CA 1
67 #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP
68 #define PCI_BAR1_ENTRY_VALID 1
69 #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \
70 | (PCI_BAR1_ENDIAN_MODE << 1) \
71 | PCI_BAR1_ENTRY_VALID)
72
73 /** Octeon Device state.
74 * Each octeon device goes through each of these states
75 * as it is initialized.
76 */
77 #define OCT_DEV_BEGIN_STATE 0x0
78 #define OCT_DEV_PCI_ENABLE_DONE 0x1
79 #define OCT_DEV_PCI_MAP_DONE 0x2
80 #define OCT_DEV_DISPATCH_INIT_DONE 0x3
81 #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x4
82 #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x5
83 #define OCT_DEV_RESP_LIST_INIT_DONE 0x6
84 #define OCT_DEV_DROQ_INIT_DONE 0x7
85 #define OCT_DEV_MBOX_SETUP_DONE 0x8
86 #define OCT_DEV_MSIX_ALLOC_VECTOR_DONE 0x9
87 #define OCT_DEV_INTR_SET_DONE 0xa
88 #define OCT_DEV_IO_QUEUES_DONE 0xb
89 #define OCT_DEV_CONSOLE_INIT_DONE 0xc
90 #define OCT_DEV_HOST_OK 0xd
91 #define OCT_DEV_CORE_OK 0xe
92 #define OCT_DEV_RUNNING 0xf
93 #define OCT_DEV_IN_RESET 0x10
94 #define OCT_DEV_STATE_INVALID 0x11
95
96 #define OCT_DEV_STATES OCT_DEV_STATE_INVALID
97
98 /** Octeon Device interrupts
99 * These interrupt bits are set in int_status filed of
100 * octeon_device structure
101 */
102 #define OCT_DEV_INTR_DMA0_FORCE 0x01
103 #define OCT_DEV_INTR_DMA1_FORCE 0x02
104 #define OCT_DEV_INTR_PKT_DATA 0x04
105
106 #define LIO_RESET_SECS (3)
107
108 /*---------------------------DISPATCH LIST-------------------------------*/
109
110 /** The dispatch list entry.
111 * The driver keeps a record of functions registered for each
112 * response header opcode in this structure. Since the opcode is
113 * hashed to index into the driver's list, more than one opcode
114 * can hash to the same entry, in which case the list field points
115 * to a linked list with the other entries.
116 */
117 struct octeon_dispatch {
118 /** List head for this entry */
119 struct list_head list;
120
121 /** The opcode for which the dispatch function & arg should be used */
122 u16 opcode;
123
124 /** The function to be called for a packet received by the driver */
125 octeon_dispatch_fn_t dispatch_fn;
126
127 /* The application specified argument to be passed to the above
128 * function along with the received packet
129 */
130 void *arg;
131 };
132
133 /** The dispatch list structure. */
134 struct octeon_dispatch_list {
135 /** access to dispatch list must be atomic */
136 spinlock_t lock;
137
138 /** Count of dispatch functions currently registered */
139 u32 count;
140
141 /** The list of dispatch functions */
142 struct octeon_dispatch *dlist;
143 };
144
145 /*----------------------- THE OCTEON DEVICE ---------------------------*/
146
147 #define OCT_MEM_REGIONS 3
148 /** PCI address space mapping information.
149 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
150 * Octeon gets mapped to different physical address spaces in
151 * the kernel.
152 */
153 struct octeon_mmio {
154 /** PCI address to which the BAR is mapped. */
155 u64 start;
156
157 /** Length of this PCI address space. */
158 u32 len;
159
160 /** Length that has been mapped to phys. address space. */
161 u32 mapped_len;
162
163 /** The physical address to which the PCI address space is mapped. */
164 u8 __iomem *hw_addr;
165
166 /** Flag indicating the mapping was successful. */
167 u32 done;
168 };
169
170 #define MAX_OCTEON_MAPS 32
171
172 struct octeon_io_enable {
173 u64 iq;
174 u64 oq;
175 u64 iq64B;
176 };
177
178 struct octeon_reg_list {
179 u32 __iomem *pci_win_wr_addr_hi;
180 u32 __iomem *pci_win_wr_addr_lo;
181 u64 __iomem *pci_win_wr_addr;
182
183 u32 __iomem *pci_win_rd_addr_hi;
184 u32 __iomem *pci_win_rd_addr_lo;
185 u64 __iomem *pci_win_rd_addr;
186
187 u32 __iomem *pci_win_wr_data_hi;
188 u32 __iomem *pci_win_wr_data_lo;
189 u64 __iomem *pci_win_wr_data;
190
191 u32 __iomem *pci_win_rd_data_hi;
192 u32 __iomem *pci_win_rd_data_lo;
193 u64 __iomem *pci_win_rd_data;
194 };
195
196 #define OCTEON_CONSOLE_MAX_READ_BYTES 512
197 typedef int (*octeon_console_print_fn)(struct octeon_device *oct,
198 u32 num, char *pre, char *suf);
199 struct octeon_console {
200 u32 active;
201 u32 waiting;
202 u64 addr;
203 u32 buffer_size;
204 u64 input_base_addr;
205 u64 output_base_addr;
206 octeon_console_print_fn print;
207 char leftover[OCTEON_CONSOLE_MAX_READ_BYTES];
208 };
209
210 struct octeon_board_info {
211 char name[OCT_BOARD_NAME];
212 char serial_number[OCT_SERIAL_LEN];
213 u64 major;
214 u64 minor;
215 };
216
217 struct octeon_fn_list {
218 void (*setup_iq_regs)(struct octeon_device *, u32);
219 void (*setup_oq_regs)(struct octeon_device *, u32);
220
221 irqreturn_t (*process_interrupt_regs)(void *);
222 u64 (*msix_interrupt_handler)(void *);
223
224 int (*setup_mbox)(struct octeon_device *);
225 int (*free_mbox)(struct octeon_device *);
226
227 int (*soft_reset)(struct octeon_device *);
228 int (*setup_device_regs)(struct octeon_device *);
229 void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int);
230 void (*bar1_idx_write)(struct octeon_device *, u32, u32);
231 u32 (*bar1_idx_read)(struct octeon_device *, u32);
232 u32 (*update_iq_read_idx)(struct octeon_instr_queue *);
233
234 void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32);
235 void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32);
236
237 void (*enable_interrupt)(struct octeon_device *, u8);
238 void (*disable_interrupt)(struct octeon_device *, u8);
239
240 int (*enable_io_queues)(struct octeon_device *);
241 void (*disable_io_queues)(struct octeon_device *);
242 };
243
244 /* Must be multiple of 8, changing breaks ABI */
245 #define CVMX_BOOTMEM_NAME_LEN 128
246
247 /* Structure for named memory blocks
248 * Number of descriptors
249 * available can be changed without affecting compatibility,
250 * but name length changes require a bump in the bootmem
251 * descriptor version
252 * Note: This structure must be naturally 64 bit aligned, as a single
253 * memory image will be used by both 32 and 64 bit programs.
254 */
255 struct cvmx_bootmem_named_block_desc {
256 /** Base address of named block */
257 u64 base_addr;
258
259 /** Size actually allocated for named block */
260 u64 size;
261
262 /** name of named block */
263 char name[CVMX_BOOTMEM_NAME_LEN];
264 };
265
266 struct oct_fw_info {
267 u32 max_nic_ports; /** max nic ports for the device */
268 u32 num_gmx_ports; /** num gmx ports */
269 u64 app_cap_flags; /** firmware cap flags */
270
271 /** The core application is running in this mode.
272 * See octeon-drv-opcodes.h for values.
273 */
274 u32 app_mode;
275 char liquidio_firmware_version[32];
276 };
277
278 /* wrappers around work structs */
279 struct cavium_wk {
280 struct delayed_work work;
281 void *ctxptr;
282 u64 ctxul;
283 };
284
285 struct cavium_wq {
286 struct workqueue_struct *wq;
287 struct cavium_wk wk;
288 };
289
290 struct octdev_props {
291 /* Each interface in the Octeon device has a network
292 * device pointer (used for OS specific calls).
293 */
294 int rx_on;
295 int napi_enabled;
296 int gmxport;
297 struct net_device *netdev;
298 };
299
300 #define LIO_FLAG_MSIX_ENABLED 0x1
301 #define MSIX_PO_INT 0x1
302 #define MSIX_PI_INT 0x2
303 #define MSIX_MBOX_INT 0x4
304
305 struct octeon_pf_vf_hs_word {
306 #ifdef __LITTLE_ENDIAN_BITFIELD
307 /** PKIND value assigned for the DPI interface */
308 u64 pkind : 8;
309
310 /** OCTEON core clock multiplier */
311 u64 core_tics_per_us : 16;
312
313 /** OCTEON coprocessor clock multiplier */
314 u64 coproc_tics_per_us : 16;
315
316 /** app that currently running on OCTEON */
317 u64 app_mode : 8;
318
319 /** RESERVED */
320 u64 reserved : 16;
321
322 #else
323
324 /** RESERVED */
325 u64 reserved : 16;
326
327 /** app that currently running on OCTEON */
328 u64 app_mode : 8;
329
330 /** OCTEON coprocessor clock multiplier */
331 u64 coproc_tics_per_us : 16;
332
333 /** OCTEON core clock multiplier */
334 u64 core_tics_per_us : 16;
335
336 /** PKIND value assigned for the DPI interface */
337 u64 pkind : 8;
338 #endif
339 };
340
341 struct octeon_sriov_info {
342 /* Number of rings assigned to VF */
343 u32 rings_per_vf;
344
345 /** Max Number of VF devices that can be enabled. This variable can
346 * specified during load time or it will be derived after allocating
347 * PF queues. When max_vfs is derived then each VF will get one queue
348 **/
349 u32 max_vfs;
350
351 /** Number of VF devices enabled using sysfs. */
352 u32 num_vfs_alloced;
353
354 /* Actual rings left for PF device */
355 u32 num_pf_rings;
356
357 /* SRN of PF usable IO queues */
358 u32 pf_srn;
359
360 /* total pf rings */
361 u32 trs;
362
363 u32 sriov_enabled;
364
365 /*lookup table that maps DPI ring number to VF pci_dev struct pointer*/
366 struct pci_dev *dpiring_to_vfpcidev_lut[MAX_POSSIBLE_VFS];
367
368 u64 vf_macaddr[MAX_POSSIBLE_VFS];
369
370 u16 vf_vlantci[MAX_POSSIBLE_VFS];
371
372 int vf_linkstate[MAX_POSSIBLE_VFS];
373
374 u64 vf_drv_loaded_mask;
375 };
376
377 struct octeon_ioq_vector {
378 struct octeon_device *oct_dev;
379 int iq_index;
380 int droq_index;
381 int vector;
382 struct octeon_mbox *mbox;
383 struct cpumask affinity_mask;
384 u32 ioq_num;
385 };
386
387 /** The Octeon device.
388 * Each Octeon device has this structure to represent all its
389 * components.
390 */
391 struct octeon_device {
392 /** Lock for PCI window configuration accesses */
393 spinlock_t pci_win_lock;
394
395 /** Lock for memory accesses */
396 spinlock_t mem_access_lock;
397
398 /** PCI device pointer */
399 struct pci_dev *pci_dev;
400
401 /** Chip specific information. */
402 void *chip;
403
404 /** Number of interfaces detected in this octeon device. */
405 u32 ifcount;
406
407 struct octdev_props props[MAX_OCTEON_LINKS];
408
409 /** Octeon Chip type. */
410 u16 chip_id;
411
412 u16 rev_id;
413
414 u16 pf_num;
415
416 u16 vf_num;
417
418 /** This device's id - set by the driver. */
419 u32 octeon_id;
420
421 /** This device's PCIe port used for traffic. */
422 u16 pcie_port;
423
424 u16 flags;
425 #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1)
426
427 /** The state of this device */
428 atomic_t status;
429
430 /** memory mapped io range */
431 struct octeon_mmio mmio[OCT_MEM_REGIONS];
432
433 struct octeon_reg_list reg_list;
434
435 struct octeon_fn_list fn_list;
436
437 struct octeon_board_info boardinfo;
438
439 u32 num_iqs;
440
441 /* The pool containing pre allocated buffers used for soft commands */
442 struct octeon_sc_buffer_pool sc_buf_pool;
443
444 /** The input instruction queues */
445 struct octeon_instr_queue *instr_queue
446 [MAX_POSSIBLE_OCTEON_INSTR_QUEUES];
447
448 /** The doubly-linked list of instruction response */
449 struct octeon_response_list response_list[MAX_RESPONSE_LISTS];
450
451 u32 num_oqs;
452
453 /** The DROQ output queues */
454 struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES];
455
456 struct octeon_io_enable io_qmask;
457
458 /** List of dispatch functions */
459 struct octeon_dispatch_list dispatch;
460
461 u32 int_status;
462
463 u64 droq_intr;
464
465 /** Physical location of the cvmx_bootmem_desc_t in octeon memory */
466 u64 bootmem_desc_addr;
467
468 /** Placeholder memory for named blocks.
469 * Assumes single-threaded access
470 */
471 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc;
472
473 /** Address of consoles descriptor */
474 u64 console_desc_addr;
475
476 /** Number of consoles available. 0 means they are inaccessible */
477 u32 num_consoles;
478
479 /* Console caches */
480 struct octeon_console console[MAX_OCTEON_MAPS];
481
482 /* Console named block info */
483 struct {
484 u64 dram_region_base;
485 int bar1_index;
486 } console_nb_info;
487
488 /* Coprocessor clock rate. */
489 u64 coproc_clock_rate;
490
491 /** The core application is running in this mode. See liquidio_common.h
492 * for values.
493 */
494 u32 app_mode;
495
496 struct oct_fw_info fw_info;
497
498 /** The name given to this device. */
499 char device_name[32];
500
501 /** Application Context */
502 void *app_ctx;
503
504 struct cavium_wq dma_comp_wq;
505
506 /** Lock for dma response list */
507 spinlock_t cmd_resp_wqlock;
508 u32 cmd_resp_state;
509
510 struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES];
511
512 struct cavium_wk nic_poll_work;
513
514 struct cavium_wk console_poll_work[MAX_OCTEON_MAPS];
515
516 void *priv;
517
518 int num_msix_irqs;
519
520 void *msix_entries;
521
522 /* when requesting IRQs, the names are stored here */
523 void *irq_name_storage;
524
525 struct octeon_sriov_info sriov_info;
526
527 struct octeon_pf_vf_hs_word pfvf_hsword;
528
529 int msix_on;
530
531 /** Mail Box details of each octeon queue. */
532 struct octeon_mbox *mbox[MAX_POSSIBLE_VFS];
533
534 /** IOq information of it's corresponding MSI-X interrupt. */
535 struct octeon_ioq_vector *ioq_vector;
536
537 int rx_pause;
538 int tx_pause;
539
540 struct oct_link_stats link_stats; /*stastics from firmware*/
541
542 /* private flags to control driver-specific features through ethtool */
543 u32 priv_flags;
544
545 void *watchdog_task;
546
547 u32 rx_coalesce_usecs;
548 u32 rx_max_coalesced_frames;
549 u32 tx_max_coalesced_frames;
550
551 bool cores_crashed;
552
553 struct {
554 int bus;
555 int dev;
556 int func;
557 } loc;
558
559 atomic_t *adapter_refcount; /* reference count of adapter */
560 bool ptp_enable;
561 };
562
563 #define OCT_DRV_ONLINE 1
564 #define OCT_DRV_OFFLINE 2
565 #define OCTEON_CN6XXX(oct) ({ \
566 typeof(oct) _oct = (oct); \
567 ((_oct->chip_id == OCTEON_CN66XX) || \
568 (_oct->chip_id == OCTEON_CN68XX)); })
569 #define OCTEON_CN23XX_PF(oct) ((oct)->chip_id == OCTEON_CN23XX_PF_VID)
570 #define OCTEON_CN23XX_VF(oct) ((oct)->chip_id == OCTEON_CN23XX_VF_VID)
571 #define CHIP_CONF(oct, TYPE) \
572 (((struct octeon_ ## TYPE *)((oct)->chip))->conf)
573
574 #define MAX_IO_PENDING_PKT_COUNT 100
575
576 /*------------------ Function Prototypes ----------------------*/
577
578 /** Initialize device list memory */
579 void octeon_init_device_list(int conf_type);
580
581 /** Free memory for Input and Output queue structures for a octeon device */
582 void octeon_free_device_mem(struct octeon_device *oct);
583
584 /* Look up a free entry in the octeon_device table and allocate resources
585 * for the octeon_device structure for an octeon device. Called at init
586 * time.
587 */
588 struct octeon_device *octeon_allocate_device(u32 pci_id,
589 u32 priv_size);
590
591 /** Register a device's bus location at initialization time.
592 * @param octeon_dev - pointer to the octeon device structure.
593 * @param bus - PCIe bus #
594 * @param dev - PCIe device #
595 * @param func - PCIe function #
596 * @param is_pf - TRUE for PF, FALSE for VF
597 * @return reference count of device's adapter
598 */
599 int octeon_register_device(struct octeon_device *oct,
600 int bus, int dev, int func, int is_pf);
601
602 /** Deregister a device at de-initialization time.
603 * @param octeon_dev - pointer to the octeon device structure.
604 * @return reference count of device's adapter
605 */
606 int octeon_deregister_device(struct octeon_device *oct);
607
608 /** Initialize the driver's dispatch list which is a mix of a hash table
609 * and a linked list. This is done at driver load time.
610 * @param octeon_dev - pointer to the octeon device structure.
611 * @return 0 on success, else -ve error value
612 */
613 int octeon_init_dispatch_list(struct octeon_device *octeon_dev);
614
615 /** Delete the driver's dispatch list and all registered entries.
616 * This is done at driver unload time.
617 * @param octeon_dev - pointer to the octeon device structure.
618 */
619 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev);
620
621 /** Initialize the core device fields with the info returned by the FW.
622 * @param recv_info - Receive info structure
623 * @param buf - Receive buffer
624 */
625 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf);
626
627 /** Gets the dispatch function registered to receive packets with a
628 * given opcode/subcode.
629 * @param octeon_dev - the octeon device pointer.
630 * @param opcode - the opcode for which the dispatch function
631 * is to checked.
632 * @param subcode - the subcode for which the dispatch function
633 * is to checked.
634 *
635 * @return Success: octeon_dispatch_fn_t (dispatch function pointer)
636 * @return Failure: NULL
637 *
638 * Looks up the dispatch list to get the dispatch function for a
639 * given opcode.
640 */
641 octeon_dispatch_fn_t
642 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
643 u16 subcode);
644
645 /** Get the octeon device pointer.
646 * @param octeon_id - The id for which the octeon device pointer is required.
647 * @return Success: Octeon device pointer.
648 * @return Failure: NULL.
649 */
650 struct octeon_device *lio_get_device(u32 octeon_id);
651
652 /** Get the octeon id assigned to the octeon device passed as argument.
653 * This function is exported to other modules.
654 * @param dev - octeon device pointer passed as a void *.
655 * @return octeon device id
656 */
657 int lio_get_device_id(void *dev);
658
OCTEON_MAJOR_REV(struct octeon_device * oct)659 static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct)
660 {
661 u16 rev = (oct->rev_id & 0xC) >> 2;
662
663 return (rev == 0) ? 1 : rev;
664 }
665
OCTEON_MINOR_REV(struct octeon_device * oct)666 static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct)
667 {
668 return oct->rev_id & 0x3;
669 }
670
671 /** Read windowed register.
672 * @param oct - pointer to the Octeon device.
673 * @param addr - Address of the register to read.
674 *
675 * This routine is called to read from the indirectly accessed
676 * Octeon registers that are visible through a PCI BAR0 mapped window
677 * register.
678 * @return - 64 bit value read from the register.
679 */
680
681 u64 lio_pci_readq(struct octeon_device *oct, u64 addr);
682
683 /** Write windowed register.
684 * @param oct - pointer to the Octeon device.
685 * @param val - Value to write
686 * @param addr - Address of the register to write
687 *
688 * This routine is called to write to the indirectly accessed
689 * Octeon registers that are visible through a PCI BAR0 mapped window
690 * register.
691 * @return Nothing.
692 */
693 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr);
694
695 /* Routines for reading and writing CSRs */
696 #define octeon_write_csr(oct_dev, reg_off, value) \
697 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
698
699 #define octeon_write_csr64(oct_dev, reg_off, val64) \
700 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
701
702 #define octeon_read_csr(oct_dev, reg_off) \
703 readl((oct_dev)->mmio[0].hw_addr + (reg_off))
704
705 #define octeon_read_csr64(oct_dev, reg_off) \
706 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
707
708 /**
709 * Checks if memory access is okay
710 *
711 * @param oct which octeon to send to
712 * @return Zero on success, negative on failure.
713 */
714 int octeon_mem_access_ok(struct octeon_device *oct);
715
716 /**
717 * Waits for DDR initialization.
718 *
719 * @param oct which octeon to send to
720 * @param timeout_in_ms pointer to how long to wait until DDR is initialized
721 * in ms.
722 * If contents are 0, it waits until contents are non-zero
723 * before starting to check.
724 * @return Zero on success, negative on failure.
725 */
726 int octeon_wait_for_ddr_init(struct octeon_device *oct,
727 u32 *timeout_in_ms);
728
729 /**
730 * Wait for u-boot to boot and be waiting for a command.
731 *
732 * @param wait_time_hundredths
733 * Maximum time to wait
734 *
735 * @return Zero on success, negative on failure.
736 */
737 int octeon_wait_for_bootloader(struct octeon_device *oct,
738 u32 wait_time_hundredths);
739
740 /**
741 * Initialize console access
742 *
743 * @param oct which octeon initialize
744 * @return Zero on success, negative on failure.
745 */
746 int octeon_init_consoles(struct octeon_device *oct);
747
748 /**
749 * Adds access to a console to the device.
750 *
751 * @param oct: which octeon to add to
752 * @param console_num: which console
753 * @param dbg_enb: ptr to debug enablement string, one of:
754 * * NULL for no debug output (i.e. disabled)
755 * * empty string enables debug output (via default method)
756 * * specific string to enable debug console output
757 *
758 * @return Zero on success, negative on failure.
759 */
760 int octeon_add_console(struct octeon_device *oct, u32 console_num,
761 char *dbg_enb);
762
763 /** write or read from a console */
764 int octeon_console_write(struct octeon_device *oct, u32 console_num,
765 char *buffer, u32 write_request_size, u32 flags);
766 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num);
767
768 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num);
769
770 /** Removes all attached consoles. */
771 void octeon_remove_consoles(struct octeon_device *oct);
772
773 /**
774 * Send a string to u-boot on console 0 as a command.
775 *
776 * @param oct which octeon to send to
777 * @param cmd_str String to send
778 * @param wait_hundredths Time to wait for u-boot to accept the command.
779 *
780 * @return Zero on success, negative on failure.
781 */
782 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str,
783 u32 wait_hundredths);
784
785 /** Parses, validates, and downloads firmware, then boots associated cores.
786 * @param oct which octeon to download firmware to
787 * @param data - The complete firmware file image
788 * @param size - The size of the data
789 *
790 * @return 0 if success.
791 * -EINVAL if file is incompatible or badly formatted.
792 * -ENODEV if no handler was found for the application type or an
793 * invalid octeon id was passed.
794 */
795 int octeon_download_firmware(struct octeon_device *oct, const u8 *data,
796 size_t size);
797
798 char *lio_get_state_string(atomic_t *state_ptr);
799
800 /** Sets up instruction queues for the device
801 * @param oct which octeon to setup
802 *
803 * @return 0 if success. 1 if fails
804 */
805 int octeon_setup_instr_queues(struct octeon_device *oct);
806
807 /** Sets up output queues for the device
808 * @param oct which octeon to setup
809 *
810 * @return 0 if success. 1 if fails
811 */
812 int octeon_setup_output_queues(struct octeon_device *oct);
813
814 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no);
815
816 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no);
817
818 /** Turns off the input and output queues for the device
819 * @param oct which octeon to disable
820 */
821 int octeon_set_io_queues_off(struct octeon_device *oct);
822
823 /** Turns on or off the given output queue for the device
824 * @param oct which octeon to change
825 * @param q_no which queue
826 * @param enable 1 to enable, 0 to disable
827 */
828 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable);
829
830 /** Retrieve the config for the device
831 * @param oct which octeon
832 * @param card_type type of card
833 *
834 * @returns pointer to configuration
835 */
836 void *oct_get_config_info(struct octeon_device *oct, u16 card_type);
837
838 /** Gets the octeon device configuration
839 * @return - pointer to the octeon configuration struture
840 */
841 struct octeon_config *octeon_get_conf(struct octeon_device *oct);
842
843 void octeon_free_ioq_vector(struct octeon_device *oct);
844 int octeon_allocate_ioq_vector(struct octeon_device *oct);
845 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq);
846
847 /* LiquidIO driver pivate flags */
848 enum {
849 OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */
850 };
851
852 #define OCT_PRIV_FLAG_DEFAULT 0x0
853
lio_get_priv_flag(struct octeon_device * octdev,u32 flag)854 static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag)
855 {
856 return !!(octdev->priv_flags & (0x1 << flag));
857 }
858
lio_set_priv_flag(struct octeon_device * octdev,u32 flag,u32 val)859 static inline void lio_set_priv_flag(struct octeon_device *octdev,
860 u32 flag, u32 val)
861 {
862 if (val)
863 octdev->priv_flags |= (0x1 << flag);
864 else
865 octdev->priv_flags &= ~(0x1 << flag);
866 }
867 #endif
868