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Searched refs:REG (Results 1 – 25 of 37) sorted by relevance

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/drivers/net/ethernet/apple/
Dmace.h13 #define REG(x) volatile unsigned char x; char x ## _pad[15] macro
16 REG(rcvfifo); /* receive FIFO */
17 REG(xmtfifo); /* transmit FIFO */
18 REG(xmtfc); /* transmit frame control */
19 REG(xmtfs); /* transmit frame status */
20 REG(xmtrc); /* transmit retry count */
21 REG(rcvfc); /* receive frame control */
22 REG(rcvfs); /* receive frame status (4 bytes) */
23 REG(fifofc); /* FIFO frame count */
24 REG(ir); /* interrupt register */
[all …]
/drivers/regulator/
Drn5t618-regulator.c31 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
51 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
52 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
53 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
54 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
56 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
57 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
58 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
59 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
60 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
[all …]
Dmc13783-regulator.c248 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
250 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
259 MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),
260 MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val),
279 MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val),
290 MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val),
291 MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val),
292 MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val),
293 MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val),
294 MC13783_GPO_DEFINE(REG, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val),
[all …]
/drivers/gpu/drm/i2c/
Dtda998x_drv.c84 #define REG(page, addr) (((page) << 8) | (addr)) macro
92 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
93 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
100 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
101 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
104 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
105 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
106 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
110 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
114 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
[all …]
/drivers/watchdog/
Dit87_wdt.c48 #define REG 0x2e macro
116 if (!request_muxed_region(REG, 2, WATCHDOG_NAME)) in superio_enter()
119 outb(0x87, REG); in superio_enter()
120 outb(0x01, REG); in superio_enter()
121 outb(0x55, REG); in superio_enter()
122 outb(0x55, REG); in superio_enter()
128 outb(0x02, REG); in superio_exit()
130 release_region(REG, 2); in superio_exit()
135 outb(LDNREG, REG); in superio_select()
141 outb(reg, REG); in superio_inb()
[all …]
Dit8712f_wdt.c61 #define REG 0x2e /* The register to read/write */ macro
99 outb(reg, REG); in superio_inb()
105 outb(reg, REG); in superio_outb()
112 outb(reg++, REG); in superio_inw()
114 outb(reg, REG); in superio_inw()
121 outb(LDN, REG); in superio_select()
130 if (!request_muxed_region(REG, 2, NAME)) in superio_enter()
133 outb(0x87, REG); in superio_enter()
134 outb(0x01, REG); in superio_enter()
135 outb(0x55, REG); in superio_enter()
[all …]
/drivers/block/
Dswim.c44 #define REG(x) unsigned char x, x ## _pad[0x200 - 1]; macro
47 REG(write_data)
48 REG(write_mark)
49 REG(write_CRC)
50 REG(write_parameter)
51 REG(write_phase)
52 REG(write_setup)
53 REG(write_mode0)
54 REG(write_mode1)
56 REG(read_data)
[all …]
Dswim3.c59 #define REG(x) unsigned char x; char x ## _pad[15]; macro
66 REG(data);
67 REG(timer); /* counts down at 1MHz */
68 REG(error);
69 REG(mode);
70 REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
71 REG(setup);
72 REG(control); /* writing bits clears them */
73 REG(status); /* writing bits sets them in control */
74 REG(intr);
[all …]
/drivers/gpio/
Dgpio-it87.c46 #define REG 0x2e macro
91 if (!request_muxed_region(REG, 2, KBUILD_MODNAME)) in superio_enter()
94 outb(0x87, REG); in superio_enter()
95 outb(0x01, REG); in superio_enter()
96 outb(0x55, REG); in superio_enter()
97 outb(0x55, REG); in superio_enter()
103 outb(0x02, REG); in superio_exit()
105 release_region(REG, 2); in superio_exit()
110 outb(LDNREG, REG); in superio_select()
116 outb(reg, REG); in superio_inb()
[all …]
/drivers/gpu/drm/tilcdc/
Dtilcdc_drv.c449 #define REG(rev, save, reg) { #reg, rev, save, reg } macro
451 REG(1, false, LCDC_PID_REG),
452 REG(1, true, LCDC_CTRL_REG),
453 REG(1, false, LCDC_STAT_REG),
454 REG(1, true, LCDC_RASTER_CTRL_REG),
455 REG(1, true, LCDC_RASTER_TIMING_0_REG),
456 REG(1, true, LCDC_RASTER_TIMING_1_REG),
457 REG(1, true, LCDC_RASTER_TIMING_2_REG),
458 REG(1, true, LCDC_DMA_CTRL_REG),
459 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
[all …]
/drivers/scsi/
Dsun3x_esp.c42 #define dma_read32(REG) \
43 readl(esp->dma_regs + (REG))
44 #define dma_write32(VAL, REG) \
45 writel((VAL), esp->dma_regs + (REG))
47 #define dma_read32(REG) \ argument
48 *(volatile u32 *)(esp->dma_regs + (REG))
49 #define dma_write32(VAL, REG) \ argument
50 do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
Dncr53c8xx.h911 #define REG(r) REGJ (nc_, r) macro
1101 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1104 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1107 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1173 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1176 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
Dmac_esp.c48 #define esp_read8(REG) mac_esp_read8(esp, REG) argument
49 #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG) argument
Dsun_esp.c30 #define dma_read32(REG) \ argument
31 sbus_readl(esp->dma_regs + (REG))
32 #define dma_write32(VAL, REG) \ argument
33 sbus_writel((VAL), esp->dma_regs + (REG))
/drivers/hwmon/
Dsmsc47b397.c54 #define REG 0x2e /* The register to read/write */ macro
59 outb(reg, REG); in superio_outb()
65 outb(reg, REG); in superio_inb()
77 if (!request_muxed_region(REG, 2, DRVNAME)) in superio_enter()
80 outb(0x55, REG); in superio_enter()
86 outb(0xAA, REG); in superio_exit()
87 release_region(REG, 2); in superio_exit()
Dsmsc47m1.c56 #define REG 0x2e /* The register to read/write */ macro
62 outb(reg, REG); in superio_outb()
69 outb(reg, REG); in superio_inb()
79 if (!request_muxed_region(REG, 2, DRVNAME)) in superio_enter()
82 outb(0x55, REG); in superio_enter()
89 outb(0xAA, REG); in superio_exit()
90 release_region(REG, 2); in superio_exit()
/drivers/pinctrl/bcm/
Dpinctrl-nsp-gpio.c82 REG, enumerator
181 nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val); in nsp_gpio_irq_ack()
198 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask); in nsp_gpio_irq_set_mask()
200 nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask); in nsp_gpio_irq_set_mask()
232 falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio); in nsp_gpio_irq_set_type()
233 level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio); in nsp_gpio_irq_set_type()
259 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling); in nsp_gpio_irq_set_type()
260 nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low); in nsp_gpio_irq_set_type()
301 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false); in nsp_gpio_direction_input()
315 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true); in nsp_gpio_direction_output()
[all …]
/drivers/iio/magnetometer/
Dmmc35240.c75 #define MMC35240_OTP_CONVERT_Y(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 6) argument
78 #define MMC35240_OTP_CONVERT_Z(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 81) argument
/drivers/net/ethernet/freescale/fs_enet/
Dmii-fec.c46 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) argument
47 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument
Dmac-fcc.c73 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) argument
74 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument
/drivers/scsi/sym53c8xx_2/
Dsym_defs.h385 #define REG(r) REGJ (nc_, r) macro
585 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
588 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
591 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
657 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
660 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
Dsym_fw.h197 #define RADDR_1(label) (RELOC_REGISTER | REG(label))
198 #define RADDR_2(label,ofs) (RELOC_REGISTER | ((REG(label))+(ofs)))
/drivers/media/dvb-frontends/
Dstb0899_priv.h255 #define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, ST… argument
/drivers/isdn/hardware/eicon/
Ddebuglib.h143 DBG_DECL(REG)
197 #define DBG_REG(args) DBG_TEST(REG, args)
Ddebuglib.c61 DBG_FUNC(REG)

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