Home
last modified time | relevance | path

Searched refs:RLC_PG_CNTL (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/radeon/
Dcik.c6413 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pu()
6419 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pu()
6427 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pd()
6433 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pd()
6440 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_cp_pg()
6446 WREG32(RLC_PG_CNTL, data); in cik_enable_cp_pg()
6453 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gds_pg()
6459 WREG32(RLC_PG_CNTL, data); in cik_enable_gds_pg()
6556 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_cgpg()
6559 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
[all …]
Dsid.h1326 #define RLC_PG_CNTL 0xC35C macro
Dcikd.h1427 #define RLC_PG_CNTL 0xC40C macro
Dsi.c5259 tmp = RREG32(RLC_PG_CNTL); in si_enable_gfx_cgpg()
5261 WREG32(RLC_PG_CNTL, tmp); in si_enable_gfx_cgpg()
5281 tmp = RREG32(RLC_PG_CNTL); in si_init_gfx_cgpg()
5283 WREG32(RLC_PG_CNTL, tmp); in si_init_gfx_cgpg()
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v8_0.c3965 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_up()
3971 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_down()
3976 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); in cz_enable_cp_power_gating()
5429 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_static_mg_power_gating()
5435 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_dynamic_mg_power_gating()
5441 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0); in polaris11_enable_gfx_quick_mg_power_gating()
5447 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0); in cz_enable_gfx_cg_power_gating()
5453 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0); in cz_enable_gfx_pipeline_power_gating()
Dsid.h1355 #define RLC_PG_CNTL 0x30D7 macro
Dgfx_v6_0.c2829 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); in gfx_v6_0_enable_gfx_cgpg()
2882 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); in gfx_v6_0_init_gfx_cgpg()