Searched refs:SD_VPCLK0_CTL (Results 1 – 7 of 7) sorted by relevance
| /drivers/staging/rts5208/ |
| D | rtsx_card.c | 685 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, in switch_ssc_clock()
687 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, in switch_ssc_clock()
802 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, in switch_normal_clock()
829 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, in switch_normal_clock()
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| D | rtsx_card.h | 799 #define SD_VPCLK0_CTL 0xFC2A macro
803 #define SD_VPTX_CTL SD_VPCLK0_CTL
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| D | sd.c | 939 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
945 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
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| /drivers/mfd/ |
| D | rtsx_usb.c | 471 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_usb_switch_clock()
473 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_usb_switch_clock()
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| D | rtsx_pcr.c | 730 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_pci_switch_clock()
732 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_pci_switch_clock()
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| /drivers/mmc/host/ |
| D | rtsx_usb_sdmmc.c | 603 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, in sd_change_phase()
609 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); in sd_change_phase()
610 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, in sd_change_phase()
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| D | rtsx_pci_sdmmc.c | 635 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); in sd_change_phase()
636 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in sd_change_phase()
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