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Searched refs:SET_VAL (Results 1 – 10 of 10) sorted by relevance

/drivers/net/ethernet/apm/xgene/
Dxgene_enet_cle.c29 *reg = SET_VAL(SB_IPFRAG, frag) | in xgene_cle_sband_to_hw()
30 SET_VAL(SB_IPPROT, type) | in xgene_cle_sband_to_hw()
31 SET_VAL(SB_IPVER, ver) | in xgene_cle_sband_to_hw()
32 SET_VAL(SB_HDRLEN, len); in xgene_cle_sband_to_hw()
40 *idt_reg = SET_VAL(IDT_DSTQID, dstqid) | in xgene_cle_idt_to_hw()
41 SET_VAL(IDT_FPSEL1, fpsel) | in xgene_cle_idt_to_hw()
42 SET_VAL(IDT_NFPSEL1, nfpsel); in xgene_cle_idt_to_hw()
44 *idt_reg = SET_VAL(IDT_DSTQID, dstqid) | in xgene_cle_idt_to_hw()
45 SET_VAL(IDT_FPSEL, fpsel) | in xgene_cle_idt_to_hw()
46 SET_VAL(IDT_NFPSEL, nfpsel); in xgene_cle_idt_to_hw()
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Dxgene_enet_ring2.c30 ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); in xgene_enet_ring_init()
33 ring_cfg[0] |= SET_VAL(X2_CFGCRID, 2); in xgene_enet_ring_init()
36 ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr); in xgene_enet_ring_init()
39 ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize) in xgene_enet_ring_init()
41 | SET_VAL(RINGADDRH, addr); in xgene_enet_ring_init()
42 ring_cfg[4] |= SET_VAL(X2_SELTHRSH, 1); in xgene_enet_ring_init()
54 ring_cfg[4] |= SET_VAL(X2_RINGTYPE, val); in xgene_enet_ring_set_type()
56 ring_cfg[3] |= SET_VAL(RINGMODE, BUFPOOL_MODE); in xgene_enet_ring_set_type()
64 ring_cfg[4] |= SET_VAL(X2_RECOMTIMEOUT, 0x7); in xgene_enet_ring_set_recombbuf()
175 data = SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK) | in xgene_enet_wr_cmd()
Dxgene_enet_main.c45 SET_VAL(FPQNUM, buf_pool->dst_ring_num) | in xgene_enet_init_bufpool()
46 SET_VAL(STASH, 3)); in xgene_enet_init_bufpool()
116 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | in xgene_enet_refill_pagepool()
117 SET_VAL(BUFDATALEN, hw_len) | in xgene_enet_refill_pagepool()
167 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | in xgene_enet_refill_bufpool()
168 SET_VAL(BUFDATALEN, bufdatalen) | in xgene_enet_refill_bufpool()
371 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index); in xgene_enet_work_msg()
379 *hopinfo |= SET_VAL(TCPHDR, l4hlen) | in xgene_enet_work_msg()
380 SET_VAL(IPHDR, l3hlen) | in xgene_enet_work_msg()
381 SET_VAL(ETHHDR, ethhdr) | in xgene_enet_work_msg()
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Dxgene_enet_xgmac.c243 data = SET_VAL(TSO_MSS1, data >> TSO_MSS1_POS) | in xgene_xgmac_set_mss()
244 SET_VAL(TSO_MSS0, mss); in xgene_xgmac_set_mss()
246 data = SET_VAL(TSO_MSS1, mss) | SET_VAL(TSO_MSS0, data); in xgene_xgmac_set_mss()
/drivers/net/phy/
Dmdio-xgene.c98 data = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg); in xgene_mdio_rgmii_read()
124 val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg); in xgene_mdio_rgmii_write()
230 val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg) | in xgene_xfi_mdio_write()
231 SET_VAL(HSTMIIMWRDAT, data); in xgene_xfi_mdio_write()
234 val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_WRITE); in xgene_xfi_mdio_write()
253 val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg); in xgene_xfi_mdio_read()
256 val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_READ); in xgene_xfi_mdio_read()
Dmdio-xgene.h116 #define SET_VAL(field, val) \ macro
/drivers/net/wireless/ath/carl9170/
Dphy.c461 SET_VAL(AR9170_PHY_SETTLING_SWITCH, val, m->switchSettling); in carl9170_init_phy_from_eeprom()
467 SET_VAL(AR9170_PHY_DESIRED_SZ_PGA, val, m->pgaDesiredSize); in carl9170_init_phy_from_eeprom()
468 SET_VAL(AR9170_PHY_DESIRED_SZ_ADC, val, m->adcDesiredSize); in carl9170_init_phy_from_eeprom()
473 SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF, val, m->txEndToXpaOff); in carl9170_init_phy_from_eeprom()
474 SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF, val, m->txEndToXpaOff); in carl9170_init_phy_from_eeprom()
475 SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAB_ON, val, m->txFrameToXpaOn); in carl9170_init_phy_from_eeprom()
476 SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAA_ON, val, m->txFrameToXpaOn); in carl9170_init_phy_from_eeprom()
481 SET_VAL(AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON, val, m->txEndToRxOn); in carl9170_init_phy_from_eeprom()
491 SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[0]); in carl9170_init_phy_from_eeprom()
497 SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[1]); in carl9170_init_phy_from_eeprom()
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Dmac.c420 SET_VAL(AR9170_MAC_BCN_DTIM, v, in carl9170_set_beacon_timers()
438 SET_VAL(AR9170_MAC_BCN_DTIM, v, in carl9170_set_beacon_timers()
463 SET_VAL(AR9170_MAC_BCN_PERIOD, v, ar->global_beacon_int); in carl9170_set_beacon_timers()
464 SET_VAL(AR9170_MAC_PRETBTT, pretbtt, ar->global_pretbtt); in carl9170_set_beacon_timers()
465 SET_VAL(AR9170_MAC_PRETBTT2, pretbtt, ar->global_pretbtt); in carl9170_set_beacon_timers()
Dtx.c785 SET_VAL(AR9170_TX_PHY_MCS, phyrate, txrate->idx); in carl9170_tx_physet()
940 SET_VAL(CARL9170_TX_SUPER_RI_TRIES, txc->s.ri[i], in carl9170_tx_apply_rateset()
997 SET_VAL(CARL9170_TX_SUPER_MISC_QUEUE, txc->s.misc, hw_queue); in carl9170_tx_prepare()
1000 SET_VAL(CARL9170_TX_SUPER_MISC_VIF_ID, txc->s.misc, cvif->id); in carl9170_tx_prepare()
1057 SET_VAL(CARL9170_TX_SUPER_AMPDU_DENSITY, in carl9170_tx_prepare()
1060 SET_VAL(CARL9170_TX_SUPER_AMPDU_FACTOR, in carl9170_tx_prepare()
1278 SET_VAL(CARL9170_TX_SUPER_MISC_QUEUE, q, in carl9170_tx_drop()
1580 SET_VAL(AR9170_MAC_BCN_HT1_PWR_CTRL, *ht1, 7); in carl9170_tx_beacon_physet()
1581 SET_VAL(AR9170_MAC_BCN_HT1_TPC, *ht1, power); in carl9170_tx_beacon_physet()
1582 SET_VAL(AR9170_MAC_BCN_HT1_CHAIN_MASK, *ht1, chains); in carl9170_tx_beacon_physet()
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Dhw.h872 #define SET_VAL(reg, value, newvalue) \ macro