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Searched refs:SSPP_VIG2 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_cfg.c36 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
120 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
204 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
366 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
Dmdp5_ctl.c326 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask()
349 case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3; in mdp_ctl_blend_ext_mask()
477 case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2; in mdp_ctl_flush_mask_pipe()
Dmdp5.xml.h71 SSPP_VIG2 = 3, enumerator
541 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]); in __offset_PIPE()
Dmdp5_kms.c763 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator