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Searched refs:TST_CFG_WRITE_ON (Results 1 – 6 of 6) sorted by relevance

/drivers/net/fddi/skfp/
Ddrvfbi.c116 outp(ADDR(B0_TST_CTRL), TST_CFG_WRITE_ON) ; /* enable for writes */ in card_start()
/drivers/net/fddi/skfp/h/
Dskfbi.h511 #define TST_CFG_WRITE_ON (1<<1) /* Bit 1: ena configuration reg. WR */ macro
/drivers/net/ethernet/marvell/
Dsky2.c711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_phy_power_up()
776 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_phy_power_down()
2367 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_qlink_intr()
2874 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_hw_intr()
2889 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_hw_intr()
3277 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_reset()
3340 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_reset()
Dsky2.h515 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ enumerator
Dskge.h252 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ enumerator
Dskge.c3338 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_error_irq()
3544 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()
3637 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()