Searched refs:UVD_CGC_CTRL (Results 1 – 8 of 8) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v5_0.c | 678 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | in uvd_v5_0_set_sw_clock_gating()
679 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); in uvd_v5_0_set_sw_clock_gating()
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| D | uvd_v6_0.c | 899 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | in uvd_v6_0_set_sw_clock_gating()
900 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); in uvd_v6_0_set_sw_clock_gating()
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| D | uvd_v7_0.c | 1514 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1515 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
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| D | sid.h | 1631 #define UVD_CGC_CTRL 0x3dc2 macro
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| /drivers/gpu/drm/radeon/ |
| D | si.c | 5172 tmp = RREG32(UVD_CGC_CTRL); in si_set_uvd_dcm()
5184 WREG32(UVD_CGC_CTRL, tmp); in si_set_uvd_dcm()
5195 u32 tmp = RREG32(UVD_CGC_CTRL); in si_init_uvd_internal_cg()
5197 WREG32(UVD_CGC_CTRL, tmp); in si_init_uvd_internal_cg()
5457 orig = data = RREG32(UVD_CGC_CTRL); in si_enable_uvd_mgcg()
5460 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
5469 orig = data = RREG32(UVD_CGC_CTRL); in si_enable_uvd_mgcg()
5472 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
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| D | sid.h | 1568 #define UVD_CGC_CTRL 0xF4B0 macro
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| D | cikd.h | 2087 #define UVD_CGC_CTRL 0xF4B0 macro
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| D | cik.c | 6268 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg()
6271 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6277 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg()
6280 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
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