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Searched refs:VCLK (Results 1 – 10 of 10) sorted by relevance

/drivers/video/fbdev/sis/
Dinit.c2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, in SiS_DoCalcDelay() argument
2272 unsigned int longtemp = VCLK * colordepth; in SiS_DoCalcDelay()
2288 SiS_CalcDelay(struct SiS_Private *SiS_Pr, unsigned short VCLK, in SiS_CalcDelay() argument
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); in SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); in SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; in SiS_SetCRT1FIFO_300() local
2313 VCLK = SiS_Pr->CSRClock; in SiS_SetCRT1FIFO_300()
2316 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT1FIFO_300()
2330 ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1; in SiS_SetCRT1FIFO_300()
2407 unsigned short i, data, VCLK, MCLK16, colorth = 0; in SiS_SetCRT1FIFO_630() local
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Dinit301.c5013 unsigned short VCLK = 0, MCLK, colorth = 0, data2 = 0; in SiS_SetCRT2FIFO_300() local
5033 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT2FIFO_300()
5045 VCLK = SiS_Pr->CSRClock_CRT1; in SiS_SetCRT2FIFO_300()
5066 data2 = temp - ((colorth * VCLK) / MCLK); in SiS_SetCRT2FIFO_300()
5123 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT2FIFO_300()
5128 VCLK = ROMAddr[0x229] | (ROMAddr[0x22a] << 8); in SiS_SetCRT2FIFO_300()
5137 VCLK = SiS_Pr->CSRClock; in SiS_SetCRT2FIFO_300()
5145 data = data * VCLK * colorth; in SiS_SetCRT2FIFO_300()
/drivers/usb/misc/sisusbvga/
Dsisusb_init.c634 unsigned short data = 0, VCLK = 0, index = 0; in SiS_SetVCLKState() local
638 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetVCLKState()
641 if (VCLK >= 166) in SiS_SetVCLKState()
645 if (VCLK >= 166) in SiS_SetVCLKState()
650 if (VCLK >= 260) in SiS_SetVCLKState()
652 else if (VCLK >= 160) in SiS_SetVCLKState()
654 else if (VCLK >= 135) in SiS_SetVCLKState()
/drivers/gpu/drm/amd/powerplay/inc/
Dpower_state.h136 uint32_t VCLK; member
/drivers/gpu/drm/amd/powerplay/hwmgr/
Dprocesspptables.c760 ps->uvd_clocks.VCLK = pnon_clock_info->ulVCLK; in init_non_clock_fields()
763 ps->uvd_clocks.VCLK = 0; in init_non_clock_fields()
Drv_hwmgr.c759 rv_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in rv_dpm_get_pp_table_entry()
Dsmu7_hwmgr.c2999 power_state->uvd_clocks.VCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3092 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in smu7_get_pp_table_entry_v1()
3240 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in smu7_get_pp_table_entry_v0()
Dcz_hwmgr.c1632 cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in cz_dpm_get_pp_table_entry()
Dvega10_hwmgr.c3039 power_state->uvd_clocks.VCLK = 0; in vega10_get_pp_table_entry_callback_func()
3106 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in vega10_get_pp_table_entry()
/drivers/staging/xgifb/
Dvb_setmode.c958 short VCLK; in XGI_SetVCLKState() local
964 VCLK = XGI_VCLKData[index].CLOCK; in XGI_SetVCLKState()
968 if (VCLK >= 200) in XGI_SetVCLKState()
979 if (VCLK < 200) in XGI_SetVCLKState()