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Searched refs:WREG32_PCIE (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dcik.c1376 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); in cik_pcie_gen3_enable()
1394 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1398 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1426 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1435 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1449 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1480 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in cik_program_aspm()
1485 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in cik_program_aspm()
1490 WREG32_PCIE(ixPCIE_P_CNTL, data); in cik_program_aspm()
1503 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm()
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Dnbio_v6_1.c180 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v6_1_update_medium_grain_clock_gating()
200 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v6_1_update_medium_grain_light_sleep()
270 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v6_1_init_registers()
Dnbio_v7_0.c147 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v7_0_update_medium_grain_clock_gating()
Dsi.c1745 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
1908 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
Damdgpu_cgs.c262 return WREG32_PCIE(index, value); in amdgpu_cgs_write_ind_register()
Dgmc_v7_0.c862 WREG32_PCIE(ixPCIE_CNTL2, data); in gmc_v7_0_enable_bif_mgls()
Dvi.c1229 WREG32_PCIE(ixPCIE_CNTL2, data); in vi_update_bif_medium_grain_light_sleep()
Damdgpu.h1635 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) macro
Damdgpu_device.c3249 WREG32_PCIE(*pos >> 2, value); in amdgpu_debugfs_regs_pcie_write()
/drivers/gpu/drm/radeon/
Dr300.c90 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); in rv370_pcie_gart_tlb_flush()
92 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush()
162 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
163 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); in rv370_pcie_gart_enable()
165 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable()
166 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable()
167 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable()
169 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); in rv370_pcie_gart_enable()
171 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); in rv370_pcie_gart_enable()
172 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); in rv370_pcie_gart_enable()
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Dsi.c5578 WREG32_PCIE(PCIE_CNTL2, data); in si_enable_bif_mgls()
7268 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
7431 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
Drv6xx_dpm.c136 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv6xx_enable_pll_sleep_in_l1()
Drv770_dpm.c127 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv770_enable_pll_sleep_in_l1()
Dradeon.h2537 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) macro