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/drivers/clk/sunxi-ng/
Dccu_div.h51 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
55 .flags = _flags, \
62 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \ argument
66 .flags = _flags, \
71 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ argument
72 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
74 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
75 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
97 _table, _gate, _flags) \ argument
107 _flags), \
[all …]
Dccu_mp.h43 _gate, _flags) \ argument
54 _flags), \
62 _flags) \ argument
67 0, _flags)
88 _flags) \ argument
101 _flags), \
Dccu_common.h33 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
35 .flags = _flags, \
42 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
44 .flags = _flags, \
52 _div, _mult, _flags) \ argument
59 _flags), \
Dccu_mux.h52 _flags) \ argument
61 _flags), \
66 _shift, _width, _gate, _flags) \ argument
69 _flags)
72 _flags) \ argument
74 _reg, _shift, _width, 0, _flags)
Dccu_nm.h45 _gate, _lock, _flags) \ argument
60 _flags), \
67 _gate, _lock, _flags) \ argument
78 _flags), \
Dccu_nkm.h47 _gate, _lock, _flags) \ argument
60 _flags), \
68 _gate, _lock, _flags) \ argument
80 _flags), \
Dccu_phase.h28 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
37 _flags), \
Dccu_gate.h27 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
35 _flags), \
Dccu_nk.h45 _flags) \ argument
58 _flags), \
Dccu_nkmp.h45 _gate, _lock, _flags) \ argument
58 _flags), \
Dccu_mult.h47 _flags) \ argument
57 _flags), \
/drivers/staging/media/atomisp/include/media/
Dlm3554.h32 _default_value, _flags) \ argument
41 .flags = (_flags),\
44 _default_value, _flags) \ argument
53 .flags = (_flags),\
58 _default_value, _flags, \ argument
63 _default_value, _flags), \
69 _default_value, _flags, \ argument
73 _default_value, _flags), \
Dlm3642.h30 _default_value, _flags) \ argument
39 .flags = (_flags),\
42 _default_value, _flags) \ argument
51 .flags = (_flags),\
56 _default_value, _flags, \ argument
61 _default_value, _flags), \
67 _default_value, _flags, \ argument
71 _default_value, _flags), \
/drivers/net/wireless/ath/ath5k/
Dath5k.h112 #define AR5K_REG_SM(_val, _flags) \ argument
113 (((_val) << _flags##_S) & (_flags))
116 #define AR5K_REG_MS(_val, _flags) \ argument
117 (((_val) & (_flags)) >> _flags##_S)
124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ argument
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
126 (((_val) << _flags##_S) & (_flags)), _reg)
128 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ argument
130 (_mask)) | (_flags), _reg)
132 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ argument
[all …]
/drivers/clk/zte/
Dclk.h17 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
19 .flags = _flags, \
26 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
28 .flags = _flags, \
/drivers/clk/
Dclk-stm32h7.c580 #define M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, _flags)\ argument
588 .flags = _flags,\
611 #define OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, _flags)\ argument
618 .flags = _flags,\
952 _rate_shift, _rate_width, _flags)\ argument
960 .flags = _flags,\
999 #define PER_CLKF(_gate_offset, _bit_idx, _name, _parent, _flags)\ argument
1005 .flags = _flags,\
1080 _flags) \ argument
1087 .flags = _flags,\
[all …]
/drivers/scsi/bfa/
Dbfad_im.h135 unsigned long _flags; \
136 spin_lock_irqsave(&(_drv)->bfad_aen_spinlock, _flags); \
140 spin_unlock_irqrestore(&(_drv)->bfad_aen_spinlock, _flags); \
/drivers/net/wireless/st/cw1200/
Dmain.c63 #define RATETAB_ENT(_rate, _rateid, _flags) \ argument
67 .flags = (_flags), \
104 #define CHAN2G(_channel, _freq, _flags) { \ argument
108 .flags = (_flags), \
113 #define CHAN5G(_channel, _flags) { \ argument
117 .flags = (_flags), \
/drivers/net/wireless/ath/ath9k/
Dcommon-init.c95 #define RATE(_bitrate, _hw_rate, _flags) { \ argument
97 .flags = (_flags), \
99 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
/drivers/clk/nxp/
Dclk-lpc32xx.c193 #define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...) \ argument
196 .flags = _flags, \
1087 #define LPC32XX_DEFINE_FIXED(_idx, _rate, _flags) \ argument
1093 .flags = (_flags), \
1114 #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \ argument
1119 .ops = (_flags & CLK_MUX_READ_ONLY ? \
1128 .flags = (_flags), \
1135 #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \ argument
1147 .flags = (_flags), \
1154 #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \ argument
[all …]
/drivers/tty/serial/8250/
D8250.h101 #define SERIAL8250_PORT_FLAGS(_base, _irq, _flags) \ argument
107 .flags = UPF_BOOT_AUTOCONF | (_flags), \
/drivers/clk/mediatek/
Dclk-mt6797.c604 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
612 .flags = _flags, \
624 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
627 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
Dclk-mtk.h91 _gate, _flags) { \ argument
102 .flags = _flags, \
Dclk-mt8173.c1033 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
1041 .flags = _flags, \
1053 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
1056 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
Dclk-mt8135.c604 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… argument
610 .flags = _flags, \

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