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Searched refs:_i (Results 1 – 25 of 34) sorted by relevance

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/drivers/infiniband/hw/i40iw/
Di40iw_register.h63 #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CO… argument
228 #define I40E_GLPE_PFAEQEDROPCNT(_i) (0x00131440 + ((_i) * 4)) /* _i=0...15 */ /* Rese… argument
232 #define I40E_GLPE_PFCEQEDROPCNT(_i) (0x001313C0 + ((_i) * 4)) /* _i=0...15 */ /* Rese… argument
236 #define I40E_GLPE_PFCQEDROPCNT(_i) (0x00131340 + ((_i) * 4)) /* _i=0...15 */ /* Reset:… argument
270 #define I40E_GLPE_VFAEQEDROPCNT(_i) (0x00132540 + ((_i) * 4)) /* _i=0...31 */ /* Rese… argument
274 #define I40E_GLPE_VFCEQEDROPCNT(_i) (0x00132440 + ((_i) * 4)) /* _i=0...31 */ /* Rese… argument
278 #define I40E_GLPE_VFCQEDROPCNT(_i) (0x00132340 + ((_i) * 4)) /* _i=0...31 */ /* Reset:… argument
282 #define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 */ /* Re… argument
288 #define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 */ /* Re… argument
292 #define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 */ /* … argument
[all …]
Di40iw_osdep.h105 #define I40E_GLHMC_VFSDCMD(_i) (0x000C8000 + ((_i) * 4)) \ argument
121 #define I40E_GLHMC_VFSDDATAHIGH(_i) (0x000C8200 + ((_i) * 4)) \ argument
128 #define I40E_GLHMC_VFSDDATALOW(_i) (0x000C8100 + ((_i) * 4)) \ argument
/drivers/net/ethernet/intel/i40e/
Di40e_register.h197 #define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER */ argument
238 #define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: GLOBR */ argument
278 #define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
313 #define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
320 #define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
331 #define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
369 #define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */ argument
402 #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */ argument
443 #define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ argument
459 #define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ argument
[all …]
/drivers/net/ethernet/intel/ixgbe/
Dixgbe_type.h245 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) argument
246 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) argument
247 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) argument
248 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) argument
258 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ argument
259 (0x012300 + (((_i) - 24) * 4)))
263 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ argument
268 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) argument
276 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ argument
277 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ argument
[all …]
/drivers/input/mouse/
Dalps.h95 #define SS4_MF_LF_V2(_b, _i) ((_b[1 + (_i) * 3] & 0x0004) == 0x0004) argument
99 #define SS4_STD_MF_X_V2(_b, _i) (((_b[0 + (_i) * 3] << 5) & 0x00E0) | \ argument
100 ((_b[1 + _i * 3] << 5) & 0x1F00) \
103 #define SS4_PLUS_STD_MF_X_V2(_b, _i) (((_b[0 + (_i) * 3] << 4) & 0x0070) | \ argument
104 ((_b[1 + (_i) * 3] << 4) & 0x0F80) \
107 #define SS4_STD_MF_Y_V2(_b, _i) (((_b[1 + (_i) * 3] << 3) & 0x0010) | \ argument
108 ((_b[2 + (_i) * 3] << 5) & 0x01E0) | \
109 ((_b[2 + (_i) * 3] << 4) & 0x0E00) \
112 #define SS4_BTL_MF_X_V2(_b, _i) (SS4_STD_MF_X_V2(_b, _i) | \ argument
113 ((_b[0 + (_i) * 3] >> 3) & 0x0010) \
[all …]
/drivers/crypto/cavium/nitrox/
Dnitrox_csr.h14 #define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000)) argument
22 #define EFL_CORE_BIST_REGX(_i) (0x1240100 + ((_i) * 0x400)) argument
26 #define PEM_BIST_STATUSX(_i) (0x1080468 | ((_i) << 18)) argument
29 #define EMU_SE_ENABLEX(_i) (0x1400000 + ((_i) * 0x40000)) argument
30 #define EMU_AE_ENABLEX(_i) (0x1400008 + ((_i) * 0x40000)) argument
31 #define EMU_WD_INT_ENA_W1SX(_i) (0x1402318 + ((_i) * 0x40000)) argument
32 #define EMU_GE_INT_ENA_W1SX(_i) (0x1402518 + ((_i) * 0x40000)) argument
33 #define EMU_FUSE_MAPX(_i) (0x1402708 + ((_i) * 0x40000)) argument
37 #define UCD_UCODE_LOAD_IDX_DATAX(_i) (0x12C0018 + ((_i) * 0x20)) argument
38 #define UCD_SE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0000 + ((_i) * 0x1000)) argument
[all …]
/drivers/net/ethernet/intel/igb/
De1000_regs.h307 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) argument
308 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
309 (0x054E0 + ((_i - 16) * 8)))
310 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
311 (0x054E4 + ((_i - 16) * 8)))
313 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) argument
314 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) argument
315 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) argument
316 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) argument
317 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) argument
[all …]
De1000_defines.h729 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) argument
743 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) argument
/drivers/net/wireless/ath/ath9k/
Dreg_wow.h127 #define AR_WOW_LEN1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3) argument
128 #define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN1_SHIFT(_i)) argument
129 #define AR_WOW_LEN2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3) argument
130 #define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN2_SHIFT(_i)) argument
131 #define AR_WOW_LEN3_SHIFT(_i) ((0xb - ((_i) & 0xb)) << 0x3) argument
132 #define AR_WOW_LENGTH3_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN3_SHIFT(_i)) argument
133 #define AR_WOW_LEN4_SHIFT(_i) ((0xf - ((_i) & 0xf)) << 0x3) argument
134 #define AR_WOW_LENGTH4_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN4_SHIFT(_i)) argument
Dar9003_phy.h622 #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \ argument
624 0x3d0 : 0x450) + ((_i) << 2))
983 #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM1_BASE + 0x450 + ((_i) << 2)) argument
1040 #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) (AR_SM2_BASE + 0x450 + ((_i) << 2)) argument
1064 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1065 …define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_… argument
1066 #define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1067 #define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1069 #define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1070 #define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
[all …]
Dar9002_phy.h190 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) argument
305 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) argument
385 #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) argument
386 #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) argument
387 #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) argument
388 #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) argument
Dreg.h382 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) argument
403 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) argument
419 #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) argument
442 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) argument
470 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) argument
506 #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) argument
520 #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) argument
540 #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) argument
559 #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) argument
575 #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) argument
[all …]
/drivers/net/ethernet/intel/i40evf/
Di40e_register.h30 #define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */ argument
34 #define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ argument
40 #define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ argument
44 #define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ argument
48 #define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ argument
160 #define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ argument
164 #define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=… argument
182 #define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ argument
188 #define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ argument
192 #define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ argument
[all …]
/drivers/net/dsa/
Dqca8k.h54 #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) argument
67 #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4)) argument
78 #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2) argument
81 #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8)) argument
84 #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8)) argument
116 #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc) argument
140 #define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100) argument
/drivers/net/ethernet/intel/e1000e/
Dregs.h122 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
123 (0x054E0 + ((_i - 16) * 8)))
124 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
125 (0x054E4 + ((_i - 16) * 8)))
126 #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) argument
127 #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) argument
237 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ argument
238 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ argument
Dich8lan.h64 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) argument
65 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) argument
140 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) argument
141 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) argument
142 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) argument
143 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) argument
144 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) argument
/drivers/gpu/drm/armada/
Darmada_crtc.h19 #define armada_reg_queue_mod(_r, _i, _v, _m, _o) \ argument
22 __reg[_i].offset = _o; \
23 __reg[_i].mask = ~(_m); \
24 __reg[_i].val = _v; \
25 _i++; \
28 #define armada_reg_queue_set(_r, _i, _v, _o) \ argument
29 armada_reg_queue_mod(_r, _i, _v, ~0, _o)
31 #define armada_reg_queue_end(_r, _i) \ argument
32 armada_reg_queue_mod(_r, _i, 0, 0, ~0)
/drivers/net/ethernet/intel/igbvf/
Dregs.h78 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
79 (0x054E0 + ((_i - 16) * 8)))
80 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
81 (0x054E4 + ((_i - 16) * 8)))
/drivers/net/wireless/ath/carl9170/
Dphy.h185 #define AR9170_PHY_REG_TIMING_CTRL4(_i) (AR9170_PHY_REG_BASE + \ argument
186 (0x0120 + ((_i) << 12)))
308 #define AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + \ argument
309 0x01b4 + ((_i) << 12))
381 #define AR9170_PHY_REG_CAL_MEAS_0(_i) (AR9170_PHY_REG_BASE + \ argument
382 0x0410 + ((_i) << 12))
383 #define AR9170_PHY_REG_CAL_MEAS_1(_i) (AR9170_PHY_REG_BASE + \ argument
384 0x0414 \ + ((_i) << 12))
385 #define AR9170_PHY_REG_CAL_MEAS_2(_i) (AR9170_PHY_REG_BASE + \ argument
386 0x0418 + ((_i) << 12))
[all …]
/drivers/net/ethernet/qlogic/qed/
Dqed_sriov.h447 #define qed_for_each_vf(_p_hwfn, _i) \ argument
448 for (_i = qed_iov_get_next_active_vf(_p_hwfn, 0); \
449 _i < MAX_NUM_VFS; \
450 _i = qed_iov_get_next_active_vf(_p_hwfn, _i + 1))
/drivers/md/bcache/
Dutil.h90 size_t _i = (h)->used++; \
91 (h)->data[_i] = d; \
93 heap_sift_down(h, _i, cmp); \
94 heap_sift(h, _i, cmp); \
273 typeof((array)->freelist) _i; \
278 for (_i = (array)->data; \
279 _i < (array)->data + ARRAY_SIZE((array)->data); \
280 _i++) \
281 array_free(array, _i); \
/drivers/staging/wlan-ng/
Dp80211metadef.h158 #define DIDmib_dot11smt_dot11WEPDefaultKeysTable_key(_i) \ argument
160 P80211DID_MKITEM(_i) | 0x0c000000)
/drivers/scsi/csiostor/
Dcsio_hw.h543 #define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i)) argument
545 #define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i)) argument
/drivers/scsi/bfa/
Dbfa_ioc.h134 #define bfa_mem_dma_sptr(_mod, _i) (&(_mod)->dma_seg[(_i)]) argument
135 #define bfa_mem_dma_seg_iter(_mod, _sptr, _nr, _i) \ argument
136 for (_i = 0, _sptr = bfa_mem_dma_sptr(_mod, _i); _i < (_nr); \
137 _i++, _sptr = bfa_mem_dma_sptr(_mod, _i))
/drivers/gpu/drm/gma500/
Dpsb_reg.h117 #define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2)) argument

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