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Searched refs:ack_irq (Results 1 – 10 of 10) sorted by relevance

/drivers/mailbox/
Dhi6220-mailbox.c70 unsigned int dir, dst_irq, ack_irq; member
195 writel(BIT(mchan->ack_irq), ACK_INT_CLR_REG(mbox->ipc)); in hi6220_mbox_interrupt()
210 writel(BIT(mchan->ack_irq), ACK_INT_ENA_REG(mbox->ipc)); in hi6220_mbox_startup()
220 writel(BIT(mchan->ack_irq), ACK_INT_DIS_REG(mbox->ipc)); in hi6220_mbox_shutdown()
221 mbox->irq_map_chan[mchan->ack_irq] = NULL; in hi6220_mbox_shutdown()
239 unsigned int ack_irq = spec->args[2]; in hi6220_mbox_xlate() local
243 ack_irq >= mbox->chan_num) { in hi6220_mbox_xlate()
246 i, dst_irq, ack_irq); in hi6220_mbox_xlate()
252 if (mbox->irq_map_chan[ack_irq] == (void *)chan) { in hi6220_mbox_xlate()
259 mchan->ack_irq = ack_irq; in hi6220_mbox_xlate()
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/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_ai.c307 adev->virt.ack_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
308 adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
321 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_ai_mailbox_add_irq_id()
337 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_get_irq()
350 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_put_irq()
Dmxgpu_vi.c565 adev->virt.ack_irq.num_types = 1; in xgpu_vi_mailbox_set_irq_funcs()
566 adev->virt.ack_irq.funcs = &xgpu_vi_mailbox_ack_irq_funcs; in xgpu_vi_mailbox_set_irq_funcs()
579 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, &adev->virt.ack_irq); in xgpu_vi_mailbox_add_irq_id()
595 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_vi_mailbox_get_irq()
608 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_vi_mailbox_put_irq()
Damdgpu_virt.h57 struct amdgpu_irq_src ack_irq; member
/drivers/misc/cxl/
Dfault.c105 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_AE, 0); in cxl_ack_ae()
129 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_R, 0); in cxl_handle_segment_miss()
194 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_R, 0); in cxl_handle_page_fault()
Dirq.c78 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_A, 0); in cxl_irq_psl9()
164 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_A, 0); in cxl_irq_psl8()
Dguest.c65 return cxl_ops->ack_irq(ctx, 0, errstat); in guest_handle_psl_slice_error()
1190 .ack_irq = guest_ack_irq,
Dnative.c1135 return cxl_ops->ack_irq(ctx, 0, errstat); in native_handle_psl_slice_error()
1552 .ack_irq = native_ack_irq,
Dcxl.h1123 int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask); member
/drivers/media/pci/cx18/
Dcx18-mailbox.c394 u32 ack_irq, req; in mb_ack_irq() local
398 ack_irq = IRQ_EPU_TO_APU_ACK; in mb_ack_irq()
402 ack_irq = IRQ_EPU_TO_CPU_ACK; in mb_ack_irq()
421 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq); in mb_ack_irq()