| /drivers/gpio/ |
| D | gpio-xgene.c | 52 u32 bit_offset; in xgene_gpio_get() local
55 bit_offset = GPIO_BIT_OFFSET(offset); in xgene_gpio_get()
56 return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); in xgene_gpio_get()
63 u32 setval, bit_offset; in __xgene_gpio_set() local
66 bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK; in __xgene_gpio_set()
70 setval |= BIT(bit_offset); in __xgene_gpio_set()
72 setval &= ~BIT(bit_offset); in __xgene_gpio_set()
89 unsigned long bank_offset, bit_offset; in xgene_gpio_get_direction() local
92 bit_offset = GPIO_BIT_OFFSET(offset); in xgene_gpio_get_direction()
94 return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); in xgene_gpio_get_direction()
[all …]
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| /drivers/acpi/acpica/ |
| D | hwregs.c | 105 if (!reg->bit_offset && reg->bit_width && in acpi_hw_get_access_bit_width()
113 ACPI_ROUND_UP_POWER_OF_TWO_8(reg->bit_offset + in acpi_hw_get_access_bit_width()
203 ACPI_ROUND_UP(reg->bit_offset + reg->bit_width, access_width); in acpi_hw_validate_register()
237 u8 bit_offset; in acpi_hw_read() local
258 bit_width = reg->bit_offset + reg->bit_width; in acpi_hw_read()
259 bit_offset = reg->bit_offset; in acpi_hw_read()
267 if (bit_offset >= access_width) { in acpi_hw_read()
269 bit_offset -= access_width; in acpi_hw_read()
332 u8 bit_offset; in acpi_hw_write() local
350 bit_width = reg->bit_offset + reg->bit_width; in acpi_hw_write()
[all …]
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| D | dsopcode.c | 117 u32 bit_offset; in acpi_ds_init_buffer_field() local
161 bit_offset = offset; in acpi_ds_init_buffer_field()
178 bit_offset = offset; in acpi_ds_init_buffer_field()
187 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
196 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
205 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
214 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
230 if ((bit_offset + bit_count) > (8 * (u32)buffer_desc->buffer.length)) { in acpi_ds_init_buffer_field()
234 acpi_ut_get_node_name(result_desc), bit_offset, in acpi_ds_init_buffer_field()
247 bit_offset, bit_count); in acpi_ds_init_buffer_field()
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| D | evgpeblk.c | 271 this_register->status_address.bit_offset = 0; in acpi_ev_create_gpe_info_blocks()
272 this_register->enable_address.bit_offset = 0; in acpi_ev_create_gpe_info_blocks()
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| /drivers/nvmem/ |
| D | core.c | 53 int bit_offset; member
339 cell->bit_offset = info->bit_offset; in nvmem_cell_info_to_nvmem_cell()
343 cell->bytes = DIV_ROUND_UP(cell->nbits + cell->bit_offset, in nvmem_cell_info_to_nvmem_cell()
824 cell->bit_offset = be32_to_cpup(addr++); in of_nvmem_cell_get()
829 cell->bytes = DIV_ROUND_UP(cell->nbits + cell->bit_offset, in of_nvmem_cell_get()
964 int i, extra, bit_offset = cell->bit_offset; in nvmem_shift_read_buffer_in_place() local
967 if (bit_offset) { in nvmem_shift_read_buffer_in_place()
969 *b++ >>= bit_offset; in nvmem_shift_read_buffer_in_place()
974 *p |= *b << (BITS_PER_BYTE - bit_offset); in nvmem_shift_read_buffer_in_place()
977 *b++ >>= bit_offset; in nvmem_shift_read_buffer_in_place()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | bit.c | 30 if (likely(bios->bit_offset)) { in bit_entry()
31 u8 entries = nvbios_rd08(bios, bios->bit_offset + 10); in bit_entry()
32 u32 entry = bios->bit_offset + 12; in bit_entry()
42 entry += nvbios_rd08(bios, bios->bit_offset + 9); in bit_entry()
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| D | base.c | 180 bios->bit_offset = nvbios_findstr(bios->data, bios->size, in nvkm_bios_new()
182 if (bios->bit_offset) in nvkm_bios_new()
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| /drivers/gpu/drm/omapdrm/ |
| D | tcm-sita.c | 97 unsigned long bit_offset = (offset > 0) ? offset / slot_bytes : 0; in l2r_t2b() local
98 unsigned long curr_bit = bit_offset; in l2r_t2b()
111 if (bit_offset > 0 && (*pos % slots_per_band != bit_offset)) { in l2r_t2b()
112 curr_bit = ALIGN(*pos, slots_per_band) + bit_offset; in l2r_t2b()
118 curr_bit = ALIGN(*pos, slot_stride) + bit_offset; in l2r_t2b()
149 if (bit_offset > 0) in l2r_t2b()
150 curr_bit = ALIGN(*pos, slots_per_band) + bit_offset; in l2r_t2b()
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| /drivers/net/wireless/ralink/rt2x00/ |
| D | rt2x00reg.h | 159 u8 bit_offset; member
164 u16 bit_offset; member
169 u32 bit_offset; member
251 ((__field).bit_offset)) & \
259 ((__field).bit_offset); \
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| D | rt73usb.c | 319 field.bit_offset = (3 * key->hw_key_idx); in rt73usb_config_shared_key()
320 field.bit_mask = 0x7 << field.bit_offset; in rt73usb_config_shared_key()
326 field.bit_offset = (3 * (key->hw_key_idx - 8)); in rt73usb_config_shared_key()
327 field.bit_mask = 0x7 << field.bit_offset; in rt73usb_config_shared_key()
2263 field.bit_offset = (queue_idx & 1) * 16; in rt73usb_conf_tx()
2264 field.bit_mask = 0xffff << field.bit_offset; in rt73usb_conf_tx()
2271 field.bit_offset = queue_idx * 4; in rt73usb_conf_tx()
2272 field.bit_mask = 0xf << field.bit_offset; in rt73usb_conf_tx()
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| D | rt61pci.c | 372 field.bit_offset = (3 * key->hw_key_idx); in rt61pci_config_shared_key()
373 field.bit_mask = 0x7 << field.bit_offset; in rt61pci_config_shared_key()
379 field.bit_offset = (3 * (key->hw_key_idx - 8)); in rt61pci_config_shared_key()
380 field.bit_mask = 0x7 << field.bit_offset; in rt61pci_config_shared_key()
2925 field.bit_offset = (queue_idx & 1) * 16; in rt61pci_conf_tx()
2926 field.bit_mask = 0xffff << field.bit_offset; in rt61pci_conf_tx()
2933 field.bit_offset = queue_idx * 4; in rt61pci_conf_tx()
2934 field.bit_mask = 0xf << field.bit_offset; in rt61pci_conf_tx()
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| /drivers/acpi/apei/ |
| D | apei-base.c | 72 *val >>= entry->register_region.bit_offset; in __apei_exec_read_register()
112 val <<= entry->register_region.bit_offset; in __apei_exec_write_register()
118 valr &= ~(entry->mask << entry->register_region.bit_offset); in __apei_exec_write_register()
582 u32 bit_width, bit_offset, access_size_code, space_id; in apei_check_gar() local
585 bit_offset = reg->bit_offset; in apei_check_gar()
592 *paddr, bit_width, bit_offset, access_size_code, in apei_check_gar()
600 *paddr, bit_width, bit_offset, access_size_code, in apei_check_gar()
607 if (bit_width == 32 && bit_offset == 0 && (*paddr & 0x03) == 0 && in apei_check_gar()
610 else if (bit_width == 64 && bit_offset == 0 && (*paddr & 0x07) == 0 && in apei_check_gar()
614 if ((bit_width + bit_offset) > *access_bit_width) { in apei_check_gar()
[all …]
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| /drivers/acpi/ |
| D | processor_throttling.c | 485 throttling->control_register.bit_offset) > 32) { in acpi_processor_get_throttling_control()
492 throttling->status_register.bit_offset) > 32) { in acpi_processor_get_throttling_control()
780 u32 bit_width, bit_offset; in acpi_read_throttling_status() local
790 bit_offset = throttling->status_register.bit_offset; in acpi_read_throttling_status()
794 (u32) (bit_width + bit_offset)); in acpi_read_throttling_status()
796 *value = (u64) ((ptc_value >> bit_offset) & ptc_mask); in acpi_read_throttling_status()
812 u32 bit_width, bit_offset; in acpi_write_throttling_state() local
822 bit_offset = throttling->control_register.bit_offset; in acpi_write_throttling_state()
828 (u32) (ptc_value << bit_offset), in acpi_write_throttling_state()
829 (u32) (bit_width + bit_offset)); in acpi_write_throttling_state()
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| /drivers/pinctrl/sprd/ |
| D | pinctrl-sprd.h | 39 .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \
56 unsigned long bit_offset; member
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| D | pinctrl-sprd.c | 116 unsigned long bit_offset; member
457 pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width); in sprd_pinconf_get()
712 << pin->bit_offset); in sprd_pinconf_set()
714 << pin->bit_offset; in sprd_pinconf_set()
782 pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width); in sprd_pinconf_get_config()
997 pin->bit_offset = sprd_soc_pin_info[i].bit_offset; in sprd_pinctrl_add_pins()
1016 pin->bit_offset, pin->bit_width, pin->reg); in sprd_pinctrl_add_pins()
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| /drivers/watchdog/ |
| D | wdat_wdt.c | 143 x >>= gas->bit_offset; in wdat_wdt_run_action()
153 x >>= gas->bit_offset; in wdat_wdt_run_action()
161 x <<= gas->bit_offset; in wdat_wdt_run_action()
166 y = y & ~(mask << gas->bit_offset); in wdat_wdt_run_action()
177 x <<= gas->bit_offset; in wdat_wdt_run_action()
182 y = y & ~(mask << gas->bit_offset); in wdat_wdt_run_action()
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| /drivers/xen/ |
| D | xen-acpi-processor.c | 85 dst_cx->reg.bit_offset = 0; in push_cxx_to_hypervisor()
91 dst_cx->reg.bit_offset = 2; in push_cxx_to_hypervisor()
205 dst_pct->bit_offset = pct->bit_offset; in xen_copy_pct_data()
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| /drivers/cpufreq/ |
| D | pcc-cpufreq.c | 56 u8 bit_offset; member
489 doorbell.bit_offset = reg_resource->bit_offset; in pcc_cpufreq_probe()
495 doorbell.space_id, doorbell.bit_width, doorbell.bit_offset, in pcc_cpufreq_probe()
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| /drivers/clk/ti/ |
| D | clkctrl.c | 54 int bit_offset; member
228 entry->bit_offset == clkspec->args[1]) { in _ti_omap4_clkctrl_xlate()
272 clkctrl_clk->bit_offset = bit; in _ti_clkctrl_clk_register()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| D | bios.h | 15 u32 bit_offset; member
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| /drivers/block/drbd/ |
| D | drbd_main.c | 1139 if (c->bit_offset >= c->bm_bits) in fill_bitmap_rle_bits()
1156 tmp = (toggle == 0) ? _drbd_bm_find_next_zero(device, c->bit_offset) in fill_bitmap_rle_bits()
1157 : _drbd_bm_find_next(device, c->bit_offset); in fill_bitmap_rle_bits()
1160 rl = tmp - c->bit_offset; in fill_bitmap_rle_bits()
1178 "t:%u bo:%lu\n", toggle, c->bit_offset); in fill_bitmap_rle_bits()
1192 c->bit_offset = tmp; in fill_bitmap_rle_bits()
1193 } while (c->bit_offset < c->bm_bits); in fill_bitmap_rle_bits()
1200 c->bit_offset -= plain_bits; in fill_bitmap_rle_bits()
1202 c->bit_offset = c->word_offset * BITS_PER_LONG; in fill_bitmap_rle_bits()
1243 if (c->bit_offset >= c->bm_bits) in send_bitmap_rle_or_plain()
[all …]
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| D | drbd_bitmap.c | 1273 unsigned long bit_offset; in __bm_find_next() local
1283 bit_offset = bm_fo & ~BITS_PER_PAGE_MASK; in __bm_find_next()
1295 bm_fo = bit_offset + i; in __bm_find_next()
1300 bm_fo = bit_offset + PAGE_SIZE*8; in __bm_find_next()
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| /drivers/staging/media/atomisp/pci/atomisp2/css2400/ |
| D | sh_css_sp.c | 1776 uint32_t bit_offset; local
1789 bit_offset = (8 * request_type) + channel_id;
1792 bit_mask = ~(1 << bit_offset);
1797 bit_val <<= bit_offset;
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| /drivers/staging/rtlwifi/phydm/ |
| D | phydm.c | 1530 u8 byte_offset, bit_offset; in phydm_set_csi_mask_reg() local
1559 bit_offset = (u8)(tone_idx_tmp & 0x7); in phydm_set_csi_mask_reg()
1571 bit_offset = (u8)(tone_idx_tmp & 0x7); in phydm_set_csi_mask_reg()
1580 reg_tmp_value |= BIT(bit_offset); in phydm_set_csi_mask_reg()
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| /drivers/irqchip/ |
| D | qcom-irq-combiner.c | 197 (reg->bit_offset != 0) || in get_registers_cb()
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