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Searched refs:control_base (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/bcm/
Dclk-iproc-pll.c84 void __iomem *control_base; member
155 (base == pll->status_base || base == pll->control_base))) in iproc_pll_write()
171 val = readl(pll->control_base + ctrl->aon.offset); in __pll_disable()
173 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); in __pll_disable()
194 val = readl(pll->control_base + ctrl->aon.offset); in __pll_enable()
196 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); in __pll_enable()
223 val = readl(pll->control_base + reset->offset); in __pll_put_in_reset()
228 iproc_pll_write(pll, pll->control_base, reset->offset, val); in __pll_put_in_reset()
239 val = readl(pll->control_base + dig_filter->offset); in __pll_bring_out_reset()
245 iproc_pll_write(pll, pll->control_base, dig_filter->offset, val); in __pll_bring_out_reset()
[all …]
/drivers/clk/keystone/
Dgate.c54 void __iomem *control_base; member
75 static void psc_config(void __iomem *control_base, void __iomem *domain_base, in psc_config() argument
81 mdctl = readl(control_base + MDCTL); in psc_config()
87 writel(mdctl, control_base + MDCTL); in psc_config()
104 mdstat = readl(control_base + MDSTAT); in psc_config()
112 u32 mdstat = readl(data->control_base + MDSTAT); in keystone_clk_is_enabled()
126 psc_config(data->control_base, data->domain_base, in keystone_clk_enable()
144 psc_config(data->control_base, data->domain_base, in keystone_clk_disable()
216 data->control_base = of_iomap(node, i); in of_psc_clk_init()
217 if (!data->control_base) { in of_psc_clk_init()
[all …]
/drivers/video/fbdev/
Dau1100fb.h70 u32 control_base; /* Mode-independent control values */ member
277 .control_base = 0x0004886A |
290 .control_base = 0x0006806A,
301 .control_base =
328 .control_base =
350 .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
362 .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
373 #define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
374 #define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
375 #define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
[all …]
Dau1100fb.c172 index = (fbdev->panel->control_base & LCD_CONTROL_SBPPF_MASK) >> LCD_CONTROL_SBPPF_BIT; in au1100fb_setmode()
188 info->var.rotate = ((fbdev->panel->control_base&LCD_CONTROL_SM_MASK) \ in au1100fb_setmode()
192 fbdev->regs->lcd_control = fbdev->panel->control_base; in au1100fb_setmode()
Dau1200fb.c1080 && (panel->control_base & LCD_CONTROL_MPI) && (pcd < 3)) { in au1200fb_fb_check_var()
/drivers/watchdog/
Dsbsa_gwdt.c96 void __iomem *control_base; member
136 gwdt->control_base + SBSA_GWDT_WOR); in sbsa_gwdt_set_timeout()
144 gwdt->control_base + SBSA_GWDT_WOR); in sbsa_gwdt_set_timeout()
160 !(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0)) in sbsa_gwdt_get_timeleft()
161 timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR); in sbsa_gwdt_get_timeleft()
163 timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) - in sbsa_gwdt_get_timeleft()
189 writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS); in sbsa_gwdt_start()
199 writel(0, gwdt->control_base + SBSA_GWDT_WCS); in sbsa_gwdt_stop()
260 gwdt->control_base = cf_base; in sbsa_gwdt_probe()