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Searched refs:cr1 (Results 1 – 14 of 14) sorted by relevance

/drivers/spi/
Dspi-sh.c86 unsigned long cr1; member
196 ss->cr1 &= ~SPI_SH_TBE; in spi_sh_send()
199 ss->cr1 & SPI_SH_TBE, in spi_sh_send()
201 if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) { in spi_sh_send()
212 ss->cr1 &= ~SPI_SH_TBE; in spi_sh_send()
215 ss->cr1 & SPI_SH_TBE, in spi_sh_send()
217 if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) { in spi_sh_send()
248 ss->cr1 &= ~SPI_SH_RBF; in spi_sh_receive()
251 ss->cr1 & SPI_SH_RBF, in spi_sh_receive()
402 unsigned long cr1; in spi_sh_irq() local
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Dspi-pxa2xx.c1018 u32 cr1; in pump_transfers() local
1146 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; in pump_transfers()
1155 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; in pump_transfers()
1190 != (cr1 & change_mask)) { in pump_transfers()
1196 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); in pump_transfers()
1209 pxa2xx_spi_write(drv_data, SSCR1, cr1); in pump_transfers()
1358 chip->cr1 = 0; in setup()
1370 chip->cr1 = SSCR1_LBM; in setup()
1408 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); in setup()
1409 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) in setup()
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Dspi-pl022.c427 u16 cr1; member
574 writew(chip->cr1, SSP_CR1(pl022->virtbase)); in restore_state()
1957 chip->cr1 = 0; in pl022_setup()
1985 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, in pl022_setup()
1995 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, in pl022_setup()
2008 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); in pl022_setup()
2009 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); in pl022_setup()
2010 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, in pl022_setup()
2012 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, in pl022_setup()
2041 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); in pl022_setup()
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Dspi-stm32.c411 u32 cr1, sr; in stm32_spi_disable() local
417 cr1 = readl_relaxed(spi->base + STM32_SPI_CR1); in stm32_spi_disable()
419 if (!(cr1 & SPI_CR1_SPE)) { in stm32_spi_disable()
428 if (cr1 & SPI_CR1_CSTART) { in stm32_spi_disable()
429 writel_relaxed(cr1 | SPI_CR1_CSUSP, in stm32_spi_disable()
Dspi-pxa2xx.h75 u32 cr1; member
/drivers/tty/serial/
Dstm32-usart.c212 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_transmit_chars_pio()
298 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_transmit_chars()
316 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_transmit_chars()
394 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_stop_tx()
416 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); in stm32_throttle()
428 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE); in stm32_unthrottle()
438 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); in stm32_stop_rx()
463 stm32_set_bits(port, ofs->cr1, val); in stm32_startup()
488 stm32_clr_bits(port, ofs->cr1, val); in stm32_shutdown()
502 u32 cr1, cr2, cr3; in stm32_set_termios() local
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Dstm32-usart.h12 u8 cr1; member
46 .cr1 = 0x0c,
62 .cr1 = 0x00,
82 .cr1 = 0x00,
Dfsl_lpuart.c1410 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; in lpuart_set_termios() local
1415 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1438 cr1 = old_cr1 & ~UARTCR1_M; in lpuart_set_termios()
1445 cr1 |= UARTCR1_M; in lpuart_set_termios()
1471 cr1 &= ~UARTCR1_PE; in lpuart_set_termios()
1477 cr1 |= UARTCR1_PE; in lpuart_set_termios()
1479 cr1 |= UARTCR1_M; in lpuart_set_termios()
1481 cr1 |= UARTCR1_PT; in lpuart_set_termios()
1483 cr1 &= ~UARTCR1_PT; in lpuart_set_termios()
1486 cr1 &= ~UARTCR1_PE; in lpuart_set_termios()
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/drivers/i2c/busses/
Di2c-stm32f4.c488 u32 cr1; in stm32f4_i2c_handle_rx_addr() local
505 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
506 cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS); in stm32f4_i2c_handle_rx_addr()
507 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
512 cr1 |= STM32F4_I2C_CR1_STOP; in stm32f4_i2c_handle_rx_addr()
514 cr1 |= STM32F4_I2C_CR1_START; in stm32f4_i2c_handle_rx_addr()
515 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
525 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
526 cr1 &= ~STM32F4_I2C_CR1_ACK; in stm32f4_i2c_handle_rx_addr()
527 cr1 |= STM32F4_I2C_CR1_POS; in stm32f4_i2c_handle_rx_addr()
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Di2c-stm32f7.c612 u32 cr1, cr2; in stm32f7_i2c_xfer_msg() local
622 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); in stm32f7_i2c_xfer_msg()
644 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | in stm32f7_i2c_xfer_msg()
648 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); in stm32f7_i2c_xfer_msg()
652 cr1 |= STM32F7_I2C_CR1_RXIE; in stm32f7_i2c_xfer_msg()
654 cr1 |= STM32F7_I2C_CR1_TXIE; in stm32f7_i2c_xfer_msg()
660 writel_relaxed(cr1, base + STM32F7_I2C_CR1); in stm32f7_i2c_xfer_msg()
/drivers/iio/trigger/
Dstm32-timer-trigger.c109 u32 ccer, cr1; in stm32_timer_start() local
139 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_timer_start()
140 if (!(cr1 & TIM_CR1_CEN)) in stm32_timer_start()
167 u32 ccer, cr1; in stm32_timer_stop() local
173 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_timer_stop()
174 if (cr1 & TIM_CR1_CEN) in stm32_timer_stop()
222 u32 psc, arr, cr1; in stm32_tt_read_frequency() local
225 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_tt_read_frequency()
229 if (cr1 & TIM_CR1_CEN) { in stm32_tt_read_frequency()
686 u32 cr1; in stm32_get_count_direction() local
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/drivers/input/touchscreen/
Dmc13783_ts.c74 int cr0, cr1; in mc13783_ts_report_sample() local
87 cr1 = (priv->sample[3] >> 12) & 0xfff; in mc13783_ts_report_sample()
91 x0, x1, x2, y0, y1, y2, cr0, cr1); in mc13783_ts_report_sample()
96 cr0 = (cr0 + cr1) / 2; in mc13783_ts_report_sample()
/drivers/mtd/devices/
Dst_spi_fsm.c1398 uint8_t sr1, cr1, dyb; in stfsm_s25fl_config() local
1448 stfsm_read_status(fsm, SPINOR_OP_RDCR, &cr1, 1); in stfsm_s25fl_config()
1451 if (!(cr1 & STFSM_S25FL_CONFIG_QE)) { in stfsm_s25fl_config()
1453 cr1 |= STFSM_S25FL_CONFIG_QE; in stfsm_s25fl_config()
1458 if (cr1 & STFSM_S25FL_CONFIG_QE) { in stfsm_s25fl_config()
1460 cr1 &= ~STFSM_S25FL_CONFIG_QE; in stfsm_s25fl_config()
1467 sta_wr = ((uint16_t)cr1 << 8) | sr1; in stfsm_s25fl_config()
/drivers/parport/
Dparport_pc.c958 int cr1, cr4, cra, cr23, cr26, cr27; in show_parconfig_smsc37c669() local
970 cr1 = inb(io + 1); in show_parconfig_smsc37c669()
987 cr1, cr4, cra, cr23, cr26, cr27); in show_parconfig_smsc37c669()
1000 (cr1 & 4) ? "yes" : "no"); in show_parconfig_smsc37c669()
1003 (cr1 & 0x08) ? "Standard mode only (SPP)" in show_parconfig_smsc37c669()