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Searched refs:cycles (Results 1 – 25 of 69) sorted by relevance

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/drivers/memory/
Djz4780-nemc.c158 uint32_t smcr, val, cycles; in jz4780_nemc_configure_bank() local
204 cycles = jz4780_nemc_ns_to_cycles(nemc, val); in jz4780_nemc_configure_bank()
205 if (cycles > 15) { in jz4780_nemc_configure_bank()
207 val, cycles); in jz4780_nemc_configure_bank()
211 smcr |= cycles << NEMC_SMCR_TAS_SHIFT; in jz4780_nemc_configure_bank()
216 cycles = jz4780_nemc_ns_to_cycles(nemc, val); in jz4780_nemc_configure_bank()
217 if (cycles > 15) { in jz4780_nemc_configure_bank()
219 val, cycles); in jz4780_nemc_configure_bank()
223 smcr |= cycles << NEMC_SMCR_TAH_SHIFT; in jz4780_nemc_configure_bank()
228 cycles = jz4780_nemc_ns_to_cycles(nemc, val); in jz4780_nemc_configure_bank()
[all …]
Dpl172.c64 int cycles; in pl172_timing_prop() local
68 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 if (cycles < 0) { in pl172_timing_prop()
70 cycles = 0; in pl172_timing_prop()
71 } else if (cycles > max) { in pl172_timing_prop()
76 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
/drivers/net/ethernet/mellanox/mlx4/
Den_clock.c44 container_of(tc, struct mlx4_en_dev, cycles); in mlx4_en_read_clock()
141 mdev->cycles.mult = neg_adj ? mult - diff : mult + diff; in mlx4_en_phc_adjfreq()
210 timecounter_init(&mdev->clock, &mdev->cycles, ns); in mlx4_en_phc_settime()
277 memset(&mdev->cycles, 0, sizeof(mdev->cycles)); in mlx4_en_init_timestamp()
278 mdev->cycles.read = mlx4_en_read_clock; in mlx4_en_init_timestamp()
279 mdev->cycles.mask = CLOCKSOURCE_MASK(48); in mlx4_en_init_timestamp()
280 mdev->cycles.shift = freq_to_shift(dev->caps.hca_core_clock); in mlx4_en_init_timestamp()
281 mdev->cycles.mult = in mlx4_en_init_timestamp()
282 clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift); in mlx4_en_init_timestamp()
283 mdev->nominal_c_mult = mdev->cycles.mult; in mlx4_en_init_timestamp()
[all …]
/drivers/net/wireless/ath/
Dhw.c144 u32 cycles, busy, rx, tx; in ath_hw_cycle_counters_update() local
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
166 common->cc_ani.cycles += cycles; in ath_hw_cycle_counters_update()
171 common->cc_survey.cycles += cycles; in ath_hw_cycle_counters_update()
183 listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) / in ath_hw_get_listen_time()
/drivers/net/ethernet/mellanox/mlx5/core/
Den_clock.c80 cycles); in mlx5e_read_internal_timer()
210 timecounter_init(&tstamp->clock, &tstamp->cycles, ns); in mlx5e_ptp_settime()
266 tstamp->cycles.mult = neg_adj ? tstamp->nominal_c_mult - diff : in mlx5e_ptp_adjfreq()
370 cycles_delta = div64_u64(nsec_delta << tstamp->cycles.shift, in mlx5e_perout_configure()
371 tstamp->cycles.mult); in mlx5e_perout_configure()
534 cycles_delta = div64_u64(nsec_delta << tstamp->cycles.shift, in mlx5e_pps_event_handler()
535 tstamp->cycles.mult); in mlx5e_pps_event_handler()
560 tstamp->cycles.read = mlx5e_read_internal_timer; in mlx5e_timestamp_init()
561 tstamp->cycles.shift = MLX5E_CYCLES_SHIFT; in mlx5e_timestamp_init()
562 tstamp->cycles.mult = clocksource_khz2mult(dev_freq, in mlx5e_timestamp_init()
[all …]
/drivers/pwm/
Dpwm-atmel.c118 unsigned long long cycles = state->period; in atmel_pwm_calculate_cprd_and_pres() local
121 cycles *= clk_get_rate(atmel_pwm->clk); in atmel_pwm_calculate_cprd_and_pres()
122 do_div(cycles, NSEC_PER_SEC); in atmel_pwm_calculate_cprd_and_pres()
124 for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1) in atmel_pwm_calculate_cprd_and_pres()
132 *cprd = cycles; in atmel_pwm_calculate_cprd_and_pres()
140 unsigned long long cycles = state->duty_cycle; in atmel_pwm_calculate_cdty() local
142 cycles *= cprd; in atmel_pwm_calculate_cdty()
143 do_div(cycles, state->period); in atmel_pwm_calculate_cdty()
144 *cdty = cprd - cycles; in atmel_pwm_calculate_cdty()
Dpwm-berlin.c90 u64 cycles, tmp; in berlin_pwm_config() local
92 cycles = clk_get_rate(pwm->clk); in berlin_pwm_config()
93 cycles *= period_ns; in berlin_pwm_config()
94 do_div(cycles, NSEC_PER_SEC); in berlin_pwm_config()
97 tmp = cycles; in berlin_pwm_config()
108 cycles = tmp * duty_ns; in berlin_pwm_config()
109 do_div(cycles, period_ns); in berlin_pwm_config()
110 duty = cycles; in berlin_pwm_config()
Dpwm-fsl-ftm.c187 unsigned long fix_rate, ext_rate, cycles; in fsl_pwm_calculate_period() local
189 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, in fsl_pwm_calculate_period()
191 if (cycles) { in fsl_pwm_calculate_period()
193 return cycles; in fsl_pwm_calculate_period()
207 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0); in fsl_pwm_calculate_period()
208 if (cycles) { in fsl_pwm_calculate_period()
210 return cycles; in fsl_pwm_calculate_period()
/drivers/cpufreq/
Dblackfin-cpufreq.c141 cycles_t cycles; in bfin_target() local
159 cycles = get_cycles(); in bfin_target()
161 cycles += 10; /* ~10 cycles we lose after get_cycles() */ in bfin_target()
162 __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index); in bfin_target()
/drivers/clocksource/
Dexynos_mct.c266 static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles) in exynos4_mct_comp0_start() argument
275 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); in exynos4_mct_comp0_start()
278 comp_cycle = exynos4_read_count_64() + cycles; in exynos4_mct_comp0_start()
288 static int exynos4_comp_set_next_event(unsigned long cycles, in exynos4_comp_set_next_event() argument
291 exynos4_mct_comp0_start(false, cycles); in exynos4_comp_set_next_event()
370 static void exynos4_mct_tick_start(unsigned long cycles, in exynos4_mct_tick_start() argument
377 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ in exynos4_mct_tick_start()
398 static int exynos4_tick_set_next_event(unsigned long cycles, in exynos4_tick_set_next_event() argument
404 exynos4_mct_tick_start(cycles, mevt); in exynos4_tick_set_next_event()
Dtimer-prima2.c77 u64 cycles; in sirfsoc_timer_read() local
82 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI); in sirfsoc_timer_read()
83 cycles = (cycles << 32) | in sirfsoc_timer_read()
86 return cycles; in sirfsoc_timer_read()
Dtimer-atlas7.c90 u64 cycles; in sirfsoc_timer_read() local
95 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI); in sirfsoc_timer_read()
96 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO); in sirfsoc_timer_read()
98 return cycles; in sirfsoc_timer_read()
Drockchip_timer.c68 static void rk_timer_update_counter(unsigned long cycles, in rk_timer_update_counter() argument
71 writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0); in rk_timer_update_counter()
80 static inline int rk_timer_set_next_event(unsigned long cycles, in rk_timer_set_next_event() argument
86 rk_timer_update_counter(cycles, timer); in rk_timer_set_next_event()
Dtegra20_timer.c64 static int tegra_timer_set_next_event(unsigned long cycles, in tegra_timer_set_next_event() argument
69 reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); in tegra_timer_set_next_event()
Dvt8500_timer.c74 static int vt8500_timer_set_next_event(unsigned long cycles, in vt8500_timer_set_next_event() argument
78 u64 alarm = clocksource.read(&clocksource) + cycles; in vt8500_timer_set_next_event()
Dcadence_ttc_timer.c116 unsigned long cycles) in ttc_set_interval() argument
125 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); in ttc_set_interval()
183 static int ttc_set_next_event(unsigned long cycles, in ttc_set_next_event() argument
189 ttc_set_interval(timer, cycles); in ttc_set_next_event()
Dsamsung_pwm_timer.c188 static int samsung_set_next_event(unsigned long cycles, in samsung_set_next_event() argument
201 if (!cycles) in samsung_set_next_event()
202 cycles = 1; in samsung_set_next_event()
204 samsung_time_setup(pwm.event_id, cycles); in samsung_set_next_event()
Dtimer-keystone.c129 static int keystone_set_next_event(unsigned long cycles, in keystone_set_next_event() argument
132 return keystone_timer_config(cycles, TCR_ENAMODE_ONESHOT_MASK); in keystone_set_next_event()
Dtimer-fttmr010.c136 static int fttmr010_timer_set_next_event(unsigned long cycles, in fttmr010_timer_set_next_event() argument
152 writel(cycles, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_next_event()
156 writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); in fttmr010_timer_set_next_event()
/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dfan.c129 u32 cycles, cur, prev; in nvkm_therm_fan_sense() local
145 cycles = 0; in nvkm_therm_fan_sense()
154 cycles++; in nvkm_therm_fan_sense()
157 } while (cycles < 5 && nvkm_timer_read(tmr) - start < 250000000); in nvkm_therm_fan_sense()
160 if (cycles == 5) { in nvkm_therm_fan_sense()
/drivers/media/usb/gspca/stv06xx/
Dstv06xx_hdcs.c185 int cycles, err; in hdcs_set_exposure() local
188 cycles = val * HDCS_CLK_FREQ_MHZ * 257; in hdcs_set_exposure()
196 rowexp = cycles / rp; in hdcs_set_exposure()
199 cycles -= rowexp * rp; in hdcs_set_exposure()
204 srowexp = hdcs->w - (cycles + hdcs->exp.er + 13) / ct; in hdcs_set_exposure()
210 srowexp = cp - hdcs->exp.er - 6 - cycles; in hdcs_set_exposure()
/drivers/firewire/
Dcore-transaction.c735 unsigned int cycles; in compute_split_timeout_timestamp() local
738 cycles = card->split_timeout_cycles; in compute_split_timeout_timestamp()
739 cycles += request_timestamp & 0x1fff; in compute_split_timeout_timestamp()
742 timestamp += (cycles / 8000) << 13; in compute_split_timeout_timestamp()
743 timestamp |= cycles % 8000; in compute_split_timeout_timestamp()
1076 unsigned int cycles; in update_split_timeout() local
1078 cycles = card->split_timeout_hi * 8000 + (card->split_timeout_lo >> 19); in update_split_timeout()
1081 cycles = clamp(cycles, 800u, 3u * 8000u); in update_split_timeout()
1083 card->split_timeout_cycles = cycles; in update_split_timeout()
1084 card->split_timeout_jiffies = DIV_ROUND_UP(cycles * HZ, 8000); in update_split_timeout()
/drivers/staging/iio/Documentation/
Dsysfs-bus-iio-impedance-analyzer-ad593327 Number of output excitation cycles (settling time cycles)
/drivers/net/wireless/ath/ath9k/
Dlink.c522 if (cc->cycles > 0) { in ath_update_survey_stats()
527 survey->time += cc->cycles / div; in ath_update_survey_stats()
533 if (cc->cycles < div) in ath_update_survey_stats()
536 if (cc->cycles > 0) in ath_update_survey_stats()
537 ret = cc->rx_busy * 100 / cc->cycles; in ath_update_survey_stats()
/drivers/net/ethernet/intel/e1000e/
Dptp.c194 u64 cycles, ns; in e1000e_phc_gettime() local
199 cycles = adapter->cc.read(&adapter->cc); in e1000e_phc_gettime()
200 ns = timecounter_cyc2time(&adapter->tc, cycles); in e1000e_phc_gettime()

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