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Searched refs:dpll_md (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/gma500/
Dcdv_intel_crt.c93 u32 adpa, dpll_md; in cdv_intel_crt_mode_set() local
108 dpll_md = REG_READ(dpll_md_reg); in cdv_intel_crt_mode_set()
110 dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); in cdv_intel_crt_mode_set()
Dcdv_device.c532 .dpll_md = DPLL_A_MD,
557 .dpll_md = DPLL_B_MD,
Dpsb_drv.h284 u32 dpll_md; member
318 u32 dpll_md; member
Dcdv_intel_display.c794 …REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_U… in cdv_intel_crtc_mode_set()
/drivers/gpu/drm/i915/
Dintel_dpll_mgr.h112 uint32_t dpll_md; member
Dintel_dpll_mgr.c454 hw_state->dpll_md, in ibx_dump_hw_state()
2529 hw_state->dpll_md, in intel_dpll_dump_hw_state()
Dintel_display.c1434 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1493 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1495 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; in chv_enable_pll()
1503 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1562 crtc->config->dpll_hw_state.dpll_md); in i9xx_enable_pll()
6636 pipe_config->dpll_hw_state.dpll_md = in vlv_compute_dpll()
6652 pipe_config->dpll_hw_state.dpll_md = in chv_compute_dpll()
6982 u32 dpll_md = (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll() local
6984 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
7642 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
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Di915_debugfs.c3476 pll->state.hw_state.dpll_md); in i915_shared_dplls_info()