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Searched refs:drm_dp_dpcd_read (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/
Ddrm_dp_helper.c250 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, in drm_dp_dpcd_read() function
275 EXPORT_SYMBOL(drm_dp_dpcd_read);
310 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, in drm_dp_dpcd_read_link_status()
333 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values)); in drm_dp_link_probe()
527 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); in drm_dp_downstream_id()
590 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); in drm_dp_downstream_debug()
595 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); in drm_dp_downstream_debug()
1010 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); in drm_dp_aux_get_crc()
1277 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); in drm_dp_read_desc()
Ddrm_dp_mst_topology.c2050 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_set_mst()
2151 sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_resume()
2167 sret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16); in drm_dp_mst_topology_mgr_resume()
2196 ret = drm_dp_dpcd_read(mgr->aux, basereg, in drm_dp_get_one_sb_msg()
2214 ret = drm_dp_dpcd_read(mgr->aux, basereg + curreply, in drm_dp_get_one_sb_msg()
2880 if (drm_dp_dpcd_read(mgr->aux, in dump_dp_payload_table()
2951 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, buf, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_dump_topology()
2953 ret = drm_dp_dpcd_read(mgr->aux, DP_FAUX_CAP, buf, 2); in drm_dp_mst_dump_topology()
2955 ret = drm_dp_dpcd_read(mgr->aux, DP_MSTM_CTRL, buf, 1); in drm_dp_mst_dump_topology()
2959 ret = drm_dp_dpcd_read(mgr->aux, DP_BRANCH_OUI, buf, DP_BRANCH_OUI_HEADER_SIZE); in drm_dp_mst_dump_topology()
Ddrm_dp_aux_dev.c164 res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo); in auxdev_read_iter()
/drivers/gpu/drm/amd/amdgpu/
Datombios_dp.c328 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) in amdgpu_atombios_dp_probe_oui()
332 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) in amdgpu_atombios_dp_probe_oui()
343 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, in amdgpu_atombios_dp_get_dpcd()
/drivers/gpu/drm/radeon/
Datombios_dp.c377 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) in radeon_dp_probe_oui()
381 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) in radeon_dp_probe_oui()
392 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, in radeon_dp_getdpcd()
Dradeon_dp_mst.c689 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg, in radeon_dp_mst_probe()
718 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, in radeon_dp_mst_check_status()
734 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, in radeon_dp_mst_check_status()
/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c470 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); in analogix_dp_process_clock_recovery()
474 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, in analogix_dp_process_clock_recovery()
542 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); in analogix_dp_process_equalizer_training()
551 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, in analogix_dp_process_equalizer_training()
/drivers/gpu/drm/i915/
Dintel_dp_aux_backlight.c63 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, in intel_dp_aux_get_backlight()
Dintel_dp.c3110 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, in intel_dp_get_link_status()
3671 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, in intel_dp_read_dpcd()
3700 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, in intel_edp_init_dpcd()
3743 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, in intel_edp_init_dpcd()
3754 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, in intel_edp_init_dpcd()
3825 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, in intel_dp_get_dpcd()
3983 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { in intel_dp_sink_crc()
4005 ret = drm_dp_dpcd_read(&intel_dp->aux, in intel_dp_get_sink_irq_esi()
4068 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, in intel_dp_autotest_video_pattern()
4075 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, in intel_dp_autotest_video_pattern()
Di915_debugfs.c4944 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); in i915_dpcd_show()
/drivers/gpu/drm/bridge/
Danalogix-anx78xx.c792 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV, in anx78xx_dp_link_training()
Dtc358767.c984 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2); in tc_main_link_setup()
/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c1196 if (drm_dp_dpcd_read(ctrl->drm_aux, DP_DPCD_REV, ctrl->dpcd, in msm_edp_ctrl_panel_connected()
/drivers/gpu/drm/nouveau/
Dnv50_display.c3276 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); in nv50_mstm_service()