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Searched refs:fp0 (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/gma500/
Dmdfld_device.c198 pipe->fp0 = PSB_RVDC32(map->fp0); in mdfld_save_display_registers()
286 PSB_WVDC32(pipe->fp0, map->fp0); in mdfld_restore_display_registers()
302 PSB_WVDC32(pipe->fp0, map->fp0); in mdfld_restore_display_registers()
449 .fp0 = MRST_FPA0,
472 .fp0 = MDFLD_DPLL_DIV0,
494 .fp0 = MRST_FPA0, /* This is what the old code did ?? */
Dpsb_intel_display.c224 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
259 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
324 fp = REG_READ(map->fp0); in psb_intel_crtc_clock_get()
333 fp = p->fp0; in psb_intel_crtc_clock_get()
Doaktrail_device.c210 p->fp0 = PSB_RVDC32(MRST_FPA0); in oaktrail_save_display_registers()
325 PSB_WVDC32(p->fp0, MRST_FPA0); in oaktrail_restore_display_registers()
465 .fp0 = MRST_FPA0,
489 .fp0 = FPB0,
Dpsb_device.c264 .fp0 = FPA0,
288 .fp0 = FPB0,
Dgma_display.c546 crtc_state->saveFP0 = REG_READ(map->fp0); in gma_crtc_save()
593 REG_WRITE(map->fp0, crtc_state->saveFP0); in gma_crtc_restore()
594 REG_READ(map->fp0); in gma_crtc_restore()
Dcdv_device.c526 .fp0 = FPA0,
551 .fp0 = FPB0,
Doaktrail_crtc.c564 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
573 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
Dpsb_drv.h278 u32 fp0; member
312 u32 fp0; member
Dcdv_intel_display.c865 fp = REG_READ(map->fp0); in cdv_intel_crtc_clock_get()
873 fp = p->fp0; in cdv_intel_crtc_clock_get()
Dmdfld_intel_display.c937 REG_WRITE(map->fp0, 0); in mdfld_crtc_mode_set()
989 REG_WRITE(map->fp0, fp); in mdfld_crtc_mode_set()
/drivers/video/fbdev/intelfb/
Dintelfbhw.c1048 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1064 fp0 = &hw->fpb0; in intelfbhw_mode_to_hw()
1076 fp0 = &hw->fpa0; in intelfbhw_mode_to_hw()
1146 *fp0 = (n << FP_N_DIVISOR_SHIFT) | in intelfbhw_mode_to_hw()
1149 *fp1 = *fp0; in intelfbhw_mode_to_hw()
1284 const u32 *dpll, *fp0, *fp1, *pipe_conf; in intelfbhw_program_mode() local
1307 fp0 = &hw->fpb0; in intelfbhw_program_mode()
1331 fp0 = &hw->fpa0; in intelfbhw_program_mode()
1406 OUTREG(fp0_reg, *fp0); in intelfbhw_program_mode()
/drivers/gpu/drm/i915/
Dintel_dpll_mgr.h113 uint32_t fp0; member
Dintel_dpll_mgr.c351 hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); in ibx_pch_dpll_get_hw_state()
362 I915_WRITE(PCH_FP0(pll->id), pll->state.hw_state.fp0); in ibx_pch_dpll_prepare()
455 hw_state->fp0, in ibx_dump_hw_state()
2530 hw_state->fp0, in intel_dpll_dump_hw_state()
Dintel_display.c5844 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
6511 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
7665 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
8341 crtc_state->dpll_hw_state.fp0 = fp; in ironlake_compute_dpll()
10155 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
10300 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); in intel_crtc_mode_get()
11354 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); in intel_pipe_config_compare()
Di915_debugfs.c3477 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); in i915_shared_dplls_info()