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Searched refs:fp1 (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/gma500/
Doaktrail_device.c211 p->fp1 = PSB_RVDC32(MRST_FPA1); in oaktrail_save_display_registers()
326 PSB_WVDC32(p->fp1, MRST_FPA1); in oaktrail_restore_display_registers()
466 .fp1 = MRST_FPA1,
490 .fp1 = FPB1,
Dpsb_device.c265 .fp1 = FPA1,
289 .fp1 = FPB1,
Dgma_display.c547 crtc_state->saveFP1 = REG_READ(map->fp1); in gma_crtc_save()
596 REG_WRITE(map->fp1, crtc_state->saveFP1); in gma_crtc_restore()
597 REG_READ(map->fp1); in gma_crtc_restore()
Dpsb_intel_display.c326 fp = REG_READ(map->fp1); in psb_intel_crtc_clock_get()
335 fp = p->fp1; in psb_intel_crtc_clock_get()
Dcdv_device.c527 .fp1 = FPA1,
552 .fp1 = FPB1,
Dpsb_drv.h279 u32 fp1; member
313 u32 fp1; member
Dcdv_intel_display.c867 fp = REG_READ(map->fp1); in cdv_intel_crtc_clock_get()
875 fp = p->fp1; in cdv_intel_crtc_clock_get()
Dmdfld_device.c450 .fp1 = MRST_FPA1,
/drivers/gpu/drm/i915/
Dintel_dpll_mgr.h114 uint32_t fp1; member
Dintel_dpll_mgr.c352 hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); in ibx_pch_dpll_get_hw_state()
363 I915_WRITE(PCH_FP1(pll->id), pll->state.hw_state.fp1); in ibx_pch_dpll_prepare()
456 hw_state->fp1); in ibx_dump_hw_state()
2531 hw_state->fp1); in intel_dpll_dump_hw_state()
Dintel_display.c5845 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
6516 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
6519 crtc_state->dpll_hw_state.fp1 = fp; in i9xx_update_pll_dividers()
7666 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
8342 crtc_state->dpll_hw_state.fp1 = fp2; in ironlake_compute_dpll()
10157 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
10301 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); in intel_crtc_mode_get()
11355 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); in intel_pipe_config_compare()
Di915_debugfs.c3478 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); in i915_shared_dplls_info()
/drivers/video/fbdev/intelfb/
Dintelfbhw.c1048 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1065 fp1 = &hw->fpb1; in intelfbhw_mode_to_hw()
1077 fp1 = &hw->fpa1; in intelfbhw_mode_to_hw()
1149 *fp1 = *fp0; in intelfbhw_mode_to_hw()
1284 const u32 *dpll, *fp0, *fp1, *pipe_conf; in intelfbhw_program_mode() local
1308 fp1 = &hw->fpb1; in intelfbhw_program_mode()
1332 fp1 = &hw->fpa1; in intelfbhw_program_mode()
1407 OUTREG(fp1_reg, *fp1); in intelfbhw_program_mode()