/drivers/infiniband/hw/hns/ |
D | hns_roce_cmd.c | 53 u32 status = readl(hr_dev->cmd.hcr + HCR_TOKEN_OFFSET); in cmd_pending() 66 u32 __iomem *hcr = (u32 *)cmd->hcr; in __hns_roce_cmd_mbox_post_hw() local 90 __raw_writeq(cpu_to_le64(in_param), hcr + 0); in __hns_roce_cmd_mbox_post_hw() 91 __raw_writeq(cpu_to_le64(out_param), hcr + 2); in __hns_roce_cmd_mbox_post_hw() 92 __raw_writel(cpu_to_le32(in_modifier), hcr + 4); in __hns_roce_cmd_mbox_post_hw() 96 __raw_writel(cpu_to_le32(val), hcr + 5); in __hns_roce_cmd_mbox_post_hw() 129 u8 __iomem *hcr = hr_dev->cmd.hcr; in __hns_roce_cmd_mbox_poll() local 153 __raw_readl(hcr + HCR_STATUS_OFFSET)); in __hns_roce_cmd_mbox_poll() 282 hr_dev->cmd.hcr = hr_dev->reg_base + ROCEE_MB1_REG; in hns_roce_cmd_init()
|
D | hns_roce_device.h | 370 u8 __iomem *hcr; member
|
/drivers/usb/serial/ |
D | ark3116.c | 71 __u32 hcr; /* handshake control register (0x8) member 146 priv->hcr = 0; in ark3116_port_probe() 213 __u8 lcr, hcr, eval; in ark3116_set_termios() local 242 hcr = (cflag & CRTSCTS) ? 0x03 : 0x00; in ark3116_set_termios() 273 __func__, hcr, lcr, quot); in ark3116_set_termios() 276 if (priv->hcr != hcr) { in ark3116_set_termios() 277 priv->hcr = hcr; in ark3116_set_termios() 278 ark3116_write_reg(serial, 0x8, hcr); in ark3116_set_termios()
|
/drivers/infiniband/hw/mthca/ |
D | mthca_cmd.c | 194 return readl(dev->hcr + HCR_STATUS_OFFSET) & in go_bit() 257 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); in mthca_cmd_post_hcr() 258 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); in mthca_cmd_post_hcr() 259 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); in mthca_cmd_post_hcr() 260 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4); in mthca_cmd_post_hcr() 261 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4); in mthca_cmd_post_hcr() 262 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4); in mthca_cmd_post_hcr() 270 op), dev->hcr + 6 * 4); in mthca_cmd_post_hcr() 373 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | in mthca_cmd_poll() 375 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); in mthca_cmd_poll() [all …]
|
D | mthca_dev.h | 323 void __iomem *hcr; member
|
/drivers/net/wireless/intersil/hostap/ |
D | hostap_cs.c | 244 static void sandisk_write_hcr(local_info_t *local, int hcr) in sandisk_write_hcr() argument 252 HFA384X_OUTB(hcr, SANDISK_HCR_OFF); in sandisk_write_hcr() 368 static void prism2_pccard_genesis_reset(local_info_t *local, int hcr) in prism2_pccard_genesis_reset() argument 378 sandisk_write_hcr(local, hcr); in prism2_pccard_genesis_reset() 399 res = pcmcia_write_config_byte(hw_priv->link, CISREG_CCSR, hcr); in prism2_pccard_genesis_reset()
|
D | hostap_download.c | 388 static int prism2_enable_genesis(local_info_t *local, int hcr) in prism2_enable_genesis() argument 395 dev->name, hcr); in prism2_enable_genesis() 398 local->func->genesis_reset(local, hcr); in prism2_enable_genesis() 407 hcr); in prism2_enable_genesis() 412 hcr, initseq[0], initseq[1], initseq[2], initseq[3], in prism2_enable_genesis()
|
D | hostap_plx.c | 296 static void prism2_plx_genesis_reset(local_info_t *local, int hcr) in prism2_plx_genesis_reset() argument 306 outb(hcr, hw_priv->cor_offset + 2); in prism2_plx_genesis_reset() 316 writeb(hcr, hw_priv->attr_mem + hw_priv->cor_offset + 2); in prism2_plx_genesis_reset()
|
D | hostap_pci.c | 267 static void prism2_pci_genesis_reset(local_info_t *local, int hcr) in prism2_pci_genesis_reset() argument 273 HFA384X_OUTW(hcr, HFA384X_PCIHCR_OFF); in prism2_pci_genesis_reset()
|
D | hostap_wlan.h | 577 void (*genesis_reset)(local_info_t *local, int hcr);
|
/drivers/net/ethernet/mellanox/mlx4/ |
D | cmd.c | 426 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET); in cmd_pending() 438 u32 __iomem *hcr = cmd->hcr; in mlx4_cmd_post() local 483 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0); in mlx4_cmd_post() 484 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1); in mlx4_cmd_post() 485 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2); in mlx4_cmd_post() 486 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3); in mlx4_cmd_post() 487 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4); in mlx4_cmd_post() 488 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5); in mlx4_cmd_post() 497 op), hcr + 6); in mlx4_cmd_post() 588 void __iomem *hcr = priv->cmd.hcr; in mlx4_cmd_poll() local [all …]
|
D | mlx4.h | 630 void __iomem *hcr; member
|
/drivers/atm/ |
D | fore200e.c | 506 if (irq_posted && (readl(fore200e->regs.pca.hcr) & PCA200E_HCR_OUTFULL)) { in fore200e_pca_irq_check() 518 writel(PCA200E_HCR_CLRINTR, fore200e->regs.pca.hcr); in fore200e_pca_irq_ack() 525 writel(PCA200E_HCR_RESET, fore200e->regs.pca.hcr); in fore200e_pca_reset() 527 writel(0, fore200e->regs.pca.hcr); in fore200e_pca_reset() 545 fore200e->regs.pca.hcr = fore200e->virt_base + PCA200E_HCR_OFFSET; in fore200e_pca_map() 748 u32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY; in fore200e_sba_irq_enable() local 749 fore200e->bus->write(hcr | SBA200E_HCR_INTR_ENA, fore200e->regs.sba.hcr); in fore200e_sba_irq_enable() 754 return fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_INTR_REQ; in fore200e_sba_irq_check() 759 u32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY; in fore200e_sba_irq_ack() local 760 fore200e->bus->write(hcr | SBA200E_HCR_INTR_CLR, fore200e->regs.sba.hcr); in fore200e_sba_irq_ack() [all …]
|
D | fore200e.h | 773 volatile u32 __iomem * hcr; /* address of host control register */ member 782 u32 __iomem *hcr; /* address of host control register */ member
|
/drivers/staging/irda/drivers/ |
D | w83977af_ir.c | 681 __u8 hcr; in w83977af_dma_receive() local 728 hcr = inb(iobase + HCR); in w83977af_dma_receive() 729 outb(hcr | HCR_EN_DMA, iobase + HCR); in w83977af_dma_receive()
|