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Searched refs:i1 (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4.xml.h353 …_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offse… in REG_MDP4_OVLP_STAGE() argument
355 …REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offse… in REG_MDP4_OVLP_STAGE_OP() argument
375 …P4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offse… in REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
377 …P4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offse… in REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
379 …OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offse… in REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument
381 …OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offse… in REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument
383 …VLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offse… in REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument
385 …VLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offse… in REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument
397 …_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_… in REG_MDP4_OVLP_STAGE_CO3() argument
399 …4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_… in REG_MDP4_OVLP_STAGE_CO3_SEL() argument
[all …]
/drivers/isdn/mISDN/
Dl1oip_codec.c324 int i1, i2, c, sample; in l1oip_4bit_alloc() local
338 i1 = 0; in l1oip_4bit_alloc()
339 while (i1 < 256) { in l1oip_4bit_alloc()
341 c = ulaw_to_4bit[i1]; in l1oip_4bit_alloc()
343 c = alaw_to_4bit[i1]; in l1oip_4bit_alloc()
346 table_com[(i1 << 8) | i2] |= (c << 4); in l1oip_4bit_alloc()
347 table_com[(i2 << 8) | i1] |= c; in l1oip_4bit_alloc()
350 i1++; in l1oip_4bit_alloc()
354 i1 = 0; in l1oip_4bit_alloc()
355 while (i1 < 16) { in l1oip_4bit_alloc()
[all …]
Ddsp_cmx.c388 int memb = 0, i, ii, i1, i2; in dsp_cmx_hardware() local
858 i1 = 0; in dsp_cmx_hardware()
860 while (i1 < ii) { in dsp_cmx_hardware()
861 if (freeslots[i1]) in dsp_cmx_hardware()
863 i1++; in dsp_cmx_hardware()
865 if (i1 == ii) { in dsp_cmx_hardware()
875 i2 = i1 + 1; in dsp_cmx_hardware()
893 member->dsp->pcm_slot_tx = i1; in dsp_cmx_hardware()
896 nextm->dsp->pcm_slot_rx = i1; in dsp_cmx_hardware()
/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5.xml.h321 …t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x… in REG_MDP5_IGC_LUT() argument
323 …G_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x… in REG_MDP5_IGC_LUT_REG() argument
374 …2_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset… in REG_MDP5_CTL_LAYER() argument
376 …REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset… in REG_MDP5_CTL_LAYER_REG() argument
509 …G_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_L… in REG_MDP5_CTL_LAYER_EXT() argument
511 …P5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_L… in REG_MDP5_CTL_LAYER_EXT_REG() argument
641 …_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x… in REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument
643 …E_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x… in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument
657 …PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x… in REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument
659 …_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x… in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument
[all …]
/drivers/video/fbdev/
Dc2p_core.h20 static inline void _transp(u32 d[], unsigned int i1, unsigned int i2, in _transp() argument
23 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; in _transp()
25 d[i1] ^= t; in _transp()
/drivers/connector/
Dcn_queue.c68 int cn_cb_equal(struct cb_id *i1, struct cb_id *i2) in cn_cb_equal() argument
70 return ((i1->idx == i2->idx) && (i1->val == i2->val)); in cn_cb_equal()
/drivers/char/hw_random/
Dn2-asm.S32 mov %i1, %o1
/drivers/staging/lustre/lustre/llite/
Dllite_lib.c2271 struct inode *i1, struct inode *i2, in ll_prep_md_op_data() argument
2280 if (namelen > ll_i2sbi(i1)->ll_namelen) in ll_prep_md_op_data()
2293 ll_i2gids(op_data->op_suppgids, i1, i2); in ll_prep_md_op_data()
2294 op_data->op_fid1 = *ll_inode2fid(i1); in ll_prep_md_op_data()
2296 if (S_ISDIR(i1->i_mode)) { in ll_prep_md_op_data()
2297 op_data->op_mea1 = ll_i2info(i1)->lli_lsm_md; in ll_prep_md_op_data()
2300 ll_i2info(i1)->lli_def_stripe_offset; in ll_prep_md_op_data()
2311 if (ll_i2sbi(i1)->ll_flags & LL_SBI_64BIT_HASH) in ll_prep_md_op_data()
2314 if (ll_need_32bit_api(ll_i2sbi(i1))) in ll_prep_md_op_data()
Dnamei.c367 void ll_i2gids(__u32 *suppgids, struct inode *i1, struct inode *i2) in ll_i2gids() argument
369 LASSERT(i1); in ll_i2gids()
371 suppgids[0] = ll_i2suppgid(i1); in ll_i2gids()
Dllite_internal.h633 void ll_i2gids(__u32 *suppgids, struct inode *i1, struct inode *i2);
830 struct inode *i1, struct inode *i2,
/drivers/block/
Dumem.c194 int i, i1; in dump_regs() local
200 for (i1 = 0; i1 < 16; i1++) in dump_regs()
/drivers/isdn/i4l/
Disdn_net.c2027 isdn_net_swap_usage(int i1, int i2) in isdn_net_swap_usage() argument
2029 int u1 = dev->usage[i1] & ISDN_USAGE_EXCLUSIVE; in isdn_net_swap_usage()
2033 printk(KERN_DEBUG "n_fi: usage of %d and %d\n", i1, i2); in isdn_net_swap_usage()
2035 dev->usage[i1] &= ~ISDN_USAGE_EXCLUSIVE; in isdn_net_swap_usage()
2036 dev->usage[i1] |= u2; in isdn_net_swap_usage()
/drivers/scsi/
Dadvansys.c349 ASC_SCSIQ_1 i1; member