1 /* 2 * Support for Intel Camera Imaging ISP subsystem. 3 * Copyright (c) 2015, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _IA_CSS_ACC_TYPES_H 16 #define _IA_CSS_ACC_TYPES_H 17 18 /** @file 19 * This file contains types used for acceleration 20 */ 21 22 #include <system_types.h> /* HAS_IRQ_MAP_VERSION_# */ 23 #include <type_support.h> 24 #include <platform_support.h> 25 #include <debug_global.h> 26 27 #include "ia_css_types.h" 28 #include "ia_css_frame_format.h" 29 30 /* Should be included without the path. 31 However, that requires adding the path to numerous makefiles 32 that have nothing to do with isp parameters. 33 */ 34 #include "runtime/isp_param/interface/ia_css_isp_param_types.h" 35 36 /* Types for the acceleration API. 37 * These should be moved to sh_css_internal.h once the old acceleration 38 * argument handling has been completed. 39 * After that, interpretation of these structures is no longer needed 40 * in the kernel and HAL. 41 */ 42 43 /** Type of acceleration. 44 */ 45 enum ia_css_acc_type { 46 IA_CSS_ACC_NONE, /**< Normal binary */ 47 IA_CSS_ACC_OUTPUT, /**< Accelerator stage on output frame */ 48 IA_CSS_ACC_VIEWFINDER, /**< Accelerator stage on viewfinder frame */ 49 IA_CSS_ACC_STANDALONE, /**< Stand-alone acceleration */ 50 }; 51 52 /** Cells types 53 */ 54 enum ia_css_cell_type { 55 IA_CSS_SP0 = 0, 56 IA_CSS_SP1, 57 IA_CSS_ISP, 58 MAX_NUM_OF_CELLS 59 }; 60 61 /** Firmware types. 62 */ 63 enum ia_css_fw_type { 64 ia_css_sp_firmware, /**< Firmware for the SP */ 65 ia_css_isp_firmware, /**< Firmware for the ISP */ 66 ia_css_bootloader_firmware, /**< Firmware for the BootLoader */ 67 ia_css_acc_firmware /**< Firmware for accelrations */ 68 }; 69 70 struct ia_css_blob_descr; 71 72 /** Blob descriptor. 73 * This structure describes an SP or ISP blob. 74 * It describes the test, data and bss sections as well as position in a 75 * firmware file. 76 * For convenience, it contains dynamic data after loading. 77 */ 78 struct ia_css_blob_info { 79 /**< Static blob data */ 80 uint32_t offset; /**< Blob offset in fw file */ 81 struct ia_css_isp_param_memory_offsets memory_offsets; /**< offset wrt hdr in bytes */ 82 uint32_t prog_name_offset; /**< offset wrt hdr in bytes */ 83 uint32_t size; /**< Size of blob */ 84 uint32_t padding_size; /**< total cummulative of bytes added due to section alignment */ 85 uint32_t icache_source; /**< Position of icache in blob */ 86 uint32_t icache_size; /**< Size of icache section */ 87 uint32_t icache_padding;/**< bytes added due to icache section alignment */ 88 uint32_t text_source; /**< Position of text in blob */ 89 uint32_t text_size; /**< Size of text section */ 90 uint32_t text_padding; /**< bytes added due to text section alignment */ 91 uint32_t data_source; /**< Position of data in blob */ 92 uint32_t data_target; /**< Start of data in SP dmem */ 93 uint32_t data_size; /**< Size of text section */ 94 uint32_t data_padding; /**< bytes added due to data section alignment */ 95 uint32_t bss_target; /**< Start position of bss in SP dmem */ 96 uint32_t bss_size; /**< Size of bss section */ 97 /**< Dynamic data filled by loader */ 98 CSS_ALIGN(const void *code, 8); /**< Code section absolute pointer within fw, code = icache + text */ 99 CSS_ALIGN(const void *data, 8); /**< Data section absolute pointer within fw, data = data + bss */ 100 }; 101 102 struct ia_css_binary_input_info { 103 uint32_t min_width; 104 uint32_t min_height; 105 uint32_t max_width; 106 uint32_t max_height; 107 uint32_t source; /* memory, sensor, variable */ 108 }; 109 110 struct ia_css_binary_output_info { 111 uint32_t min_width; 112 uint32_t min_height; 113 uint32_t max_width; 114 uint32_t max_height; 115 uint32_t num_chunks; 116 uint32_t variable_format; 117 }; 118 119 struct ia_css_binary_internal_info { 120 uint32_t max_width; 121 uint32_t max_height; 122 }; 123 124 struct ia_css_binary_bds_info { 125 uint32_t supported_bds_factors; 126 }; 127 128 struct ia_css_binary_dvs_info { 129 uint32_t max_envelope_width; 130 uint32_t max_envelope_height; 131 }; 132 133 struct ia_css_binary_vf_dec_info { 134 uint32_t is_variable; 135 uint32_t max_log_downscale; 136 }; 137 138 struct ia_css_binary_s3a_info { 139 uint32_t s3atbl_use_dmem; 140 uint32_t fixed_s3a_deci_log; 141 }; 142 143 /** DPC related binary info */ 144 struct ia_css_binary_dpc_info { 145 uint32_t bnr_lite; /**< bnr lite enable flag */ 146 }; 147 148 struct ia_css_binary_iterator_info { 149 uint32_t num_stripes; 150 uint32_t row_stripes_height; 151 uint32_t row_stripes_overlap_lines; 152 }; 153 154 struct ia_css_binary_address_info { 155 uint32_t isp_addresses; /* Address in ISP dmem */ 156 uint32_t main_entry; /* Address of entry fct */ 157 uint32_t in_frame; /* Address in ISP dmem */ 158 uint32_t out_frame; /* Address in ISP dmem */ 159 uint32_t in_data; /* Address in ISP dmem */ 160 uint32_t out_data; /* Address in ISP dmem */ 161 uint32_t sh_dma_cmd_ptr; /* In ISP dmem */ 162 }; 163 164 struct ia_css_binary_uds_info { 165 uint16_t bpp; 166 uint16_t use_bci; 167 uint16_t use_str; 168 uint16_t woix; 169 uint16_t woiy; 170 uint16_t extra_out_vecs; 171 uint16_t vectors_per_line_in; 172 uint16_t vectors_per_line_out; 173 uint16_t vectors_c_per_line_in; 174 uint16_t vectors_c_per_line_out; 175 uint16_t vmem_gdc_in_block_height_y; 176 uint16_t vmem_gdc_in_block_height_c; 177 /* uint16_t padding; */ 178 }; 179 180 struct ia_css_binary_pipeline_info { 181 uint32_t mode; 182 uint32_t isp_pipe_version; 183 uint32_t pipelining; 184 uint32_t c_subsampling; 185 uint32_t top_cropping; 186 uint32_t left_cropping; 187 uint32_t variable_resolution; 188 }; 189 190 struct ia_css_binary_block_info { 191 uint32_t block_width; 192 uint32_t block_height; 193 uint32_t output_block_height; 194 }; 195 196 /** Structure describing an ISP binary. 197 * It describes the capabilities of a binary, like the maximum resolution, 198 * support features, dma channels, uds features, etc. 199 * This part is to be used by the SP. 200 * Future refactoring should move binary properties to ia_css_binary_xinfo, 201 * thereby making the SP code more binary independent. 202 */ 203 struct ia_css_binary_info { 204 CSS_ALIGN(uint32_t id, 8); /* IA_CSS_BINARY_ID_* */ 205 struct ia_css_binary_pipeline_info pipeline; 206 struct ia_css_binary_input_info input; 207 struct ia_css_binary_output_info output; 208 struct ia_css_binary_internal_info internal; 209 struct ia_css_binary_bds_info bds; 210 struct ia_css_binary_dvs_info dvs; 211 struct ia_css_binary_vf_dec_info vf_dec; 212 struct ia_css_binary_s3a_info s3a; 213 struct ia_css_binary_dpc_info dpc_bnr; /**< DPC related binary info */ 214 struct ia_css_binary_iterator_info iterator; 215 struct ia_css_binary_address_info addresses; 216 struct ia_css_binary_uds_info uds; 217 struct ia_css_binary_block_info block; 218 struct ia_css_isp_param_isp_segments mem_initializers; 219 /* MW: Packing (related) bools in an integer ?? */ 220 struct { 221 #ifdef ISP2401 222 uint8_t luma_only; 223 uint8_t input_yuv; 224 uint8_t input_raw; 225 #endif 226 uint8_t reduced_pipe; 227 uint8_t vf_veceven; 228 uint8_t dis; 229 uint8_t dvs_envelope; 230 uint8_t uds; 231 uint8_t dvs_6axis; 232 uint8_t block_output; 233 uint8_t streaming_dma; 234 uint8_t ds; 235 uint8_t bayer_fir_6db; 236 uint8_t raw_binning; 237 uint8_t continuous; 238 uint8_t s3a; 239 uint8_t fpnr; 240 uint8_t sc; 241 uint8_t macc; 242 uint8_t output; 243 uint8_t ref_frame; 244 uint8_t tnr; 245 uint8_t xnr; 246 uint8_t params; 247 uint8_t ca_gdc; 248 uint8_t isp_addresses; 249 uint8_t in_frame; 250 uint8_t out_frame; 251 uint8_t high_speed; 252 uint8_t dpc; 253 uint8_t padding[2]; 254 } enable; 255 struct { 256 /* DMA channel ID: [0,...,HIVE_ISP_NUM_DMA_CHANNELS> */ 257 uint8_t ref_y_channel; 258 uint8_t ref_c_channel; 259 uint8_t tnr_channel; 260 uint8_t tnr_out_channel; 261 uint8_t dvs_coords_channel; 262 uint8_t output_channel; 263 uint8_t c_channel; 264 uint8_t vfout_channel; 265 uint8_t vfout_c_channel; 266 uint8_t vfdec_bits_per_pixel; 267 uint8_t claimed_by_isp; 268 uint8_t padding[2]; 269 } dma; 270 }; 271 272 /** Structure describing an ISP binary. 273 * It describes the capabilities of a binary, like the maximum resolution, 274 * support features, dma channels, uds features, etc. 275 */ 276 struct ia_css_binary_xinfo { 277 /* Part that is of interest to the SP. */ 278 struct ia_css_binary_info sp; 279 280 /* Rest of the binary info, only interesting to the host. */ 281 enum ia_css_acc_type type; 282 CSS_ALIGN(int32_t num_output_formats, 8); 283 enum ia_css_frame_format output_formats[IA_CSS_FRAME_FORMAT_NUM]; 284 CSS_ALIGN(int32_t num_vf_formats, 8); /**< number of supported vf formats */ 285 enum ia_css_frame_format vf_formats[IA_CSS_FRAME_FORMAT_NUM]; /**< types of supported vf formats */ 286 uint8_t num_output_pins; 287 ia_css_ptr xmem_addr; 288 CSS_ALIGN(const struct ia_css_blob_descr *blob, 8); 289 CSS_ALIGN(uint32_t blob_index, 8); 290 CSS_ALIGN(union ia_css_all_memory_offsets mem_offsets, 8); 291 CSS_ALIGN(struct ia_css_binary_xinfo *next, 8); 292 }; 293 294 /** Structure describing the Bootloader (an ISP binary). 295 * It contains several address, either in ddr, isp_dmem or 296 * the entry function in icache. 297 */ 298 struct ia_css_bl_info { 299 uint32_t num_dma_cmds; /**< Number of cmds sent by CSS */ 300 uint32_t dma_cmd_list; /**< Dma command list sent by CSS */ 301 uint32_t sw_state; /**< Polled from css */ 302 /* Entry functions */ 303 uint32_t bl_entry; /**< The SP entry function */ 304 }; 305 306 /** Structure describing the SP binary. 307 * It contains several address, either in ddr, sp_dmem or 308 * the entry function in pmem. 309 */ 310 struct ia_css_sp_info { 311 uint32_t init_dmem_data; /**< data sect config, stored to dmem */ 312 uint32_t per_frame_data; /**< Per frame data, stored to dmem */ 313 uint32_t group; /**< Per pipeline data, loaded by dma */ 314 uint32_t output; /**< SP output data, loaded by dmem */ 315 uint32_t host_sp_queue; /**< Host <-> SP queues */ 316 uint32_t host_sp_com;/**< Host <-> SP commands */ 317 uint32_t isp_started; /**< Polled from sensor thread, csim only */ 318 uint32_t sw_state; /**< Polled from css */ 319 uint32_t host_sp_queues_initialized; /**< Polled from the SP */ 320 uint32_t sleep_mode; /**< different mode to halt SP */ 321 uint32_t invalidate_tlb; /**< inform SP to invalidate mmu TLB */ 322 #ifndef ISP2401 323 uint32_t stop_copy_preview; /**< suspend copy and preview pipe when capture */ 324 #endif 325 uint32_t debug_buffer_ddr_address; /**< inform SP the address 326 of DDR debug queue */ 327 uint32_t perf_counter_input_system_error; /**< input system perf 328 counter array */ 329 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG 330 uint32_t debug_wait; /**< thread/pipe post mortem debug */ 331 uint32_t debug_stage; /**< thread/pipe post mortem debug */ 332 uint32_t debug_stripe; /**< thread/pipe post mortem debug */ 333 #endif 334 uint32_t threads_stack; /**< sp thread's stack pointers */ 335 uint32_t threads_stack_size; /**< sp thread's stack sizes */ 336 uint32_t curr_binary_id; /**< current binary id */ 337 uint32_t raw_copy_line_count; /**< raw copy line counter */ 338 uint32_t ddr_parameter_address; /**< acc param ddrptr, sp dmem */ 339 uint32_t ddr_parameter_size; /**< acc param size, sp dmem */ 340 /* Entry functions */ 341 uint32_t sp_entry; /**< The SP entry function */ 342 uint32_t tagger_frames_addr; /**< Base address of tagger state */ 343 }; 344 345 /* The following #if is there because this header file is also included 346 by SP and ISP code but they do not need this data and HIVECC has alignment 347 issue with the firmware struct/union's. 348 More permanent solution will be to refactor this include. 349 */ 350 #if !defined(__ISP) 351 /** Accelerator firmware information. 352 */ 353 struct ia_css_acc_info { 354 uint32_t per_frame_data; /**< Dummy for now */ 355 }; 356 357 /** Firmware information. 358 */ 359 union ia_css_fw_union { 360 struct ia_css_binary_xinfo isp; /**< ISP info */ 361 struct ia_css_sp_info sp; /**< SP info */ 362 struct ia_css_bl_info bl; /**< Bootloader info */ 363 struct ia_css_acc_info acc; /**< Accelerator info */ 364 }; 365 366 /** Firmware information. 367 */ 368 struct ia_css_fw_info { 369 size_t header_size; /**< size of fw header */ 370 CSS_ALIGN(uint32_t type, 8); 371 union ia_css_fw_union info; /**< Binary info */ 372 struct ia_css_blob_info blob; /**< Blob info */ 373 /* Dynamic part */ 374 struct ia_css_fw_info *next; 375 CSS_ALIGN(uint32_t loaded, 8); /**< Firmware has been loaded */ 376 CSS_ALIGN(const uint8_t *isp_code, 8); /**< ISP pointer to code */ 377 /**< Firmware handle between user space and kernel */ 378 CSS_ALIGN(uint32_t handle, 8); 379 /**< Sections to copy from/to ISP */ 380 struct ia_css_isp_param_css_segments mem_initializers; 381 /**< Initializer for local ISP memories */ 382 }; 383 384 struct ia_css_blob_descr { 385 const unsigned char *blob; 386 struct ia_css_fw_info header; 387 const char *name; 388 union ia_css_all_memory_offsets mem_offsets; 389 }; 390 391 struct ia_css_acc_fw; 392 393 /** Structure describing the SP binary of a stand-alone accelerator. 394 */ 395 struct ia_css_acc_sp { 396 void (*init)(struct ia_css_acc_fw *); /**< init for crun */ 397 uint32_t sp_prog_name_offset; /**< program name offset wrt hdr in bytes */ 398 uint32_t sp_blob_offset; /**< blob offset wrt hdr in bytes */ 399 void *entry; /**< Address of sp entry point */ 400 uint32_t *css_abort; /**< SP dmem abort flag */ 401 void *isp_code; /**< SP dmem address holding xmem 402 address of isp code */ 403 struct ia_css_fw_info fw; /**< SP fw descriptor */ 404 const uint8_t *code; /**< ISP pointer of allocated SP code */ 405 }; 406 407 /** Acceleration firmware descriptor. 408 * This descriptor descibes either SP code (stand-alone), or 409 * ISP code (a separate pipeline stage). 410 */ 411 struct ia_css_acc_fw_hdr { 412 enum ia_css_acc_type type; /**< Type of accelerator */ 413 uint32_t isp_prog_name_offset; /**< program name offset wrt 414 header in bytes */ 415 uint32_t isp_blob_offset; /**< blob offset wrt header 416 in bytes */ 417 uint32_t isp_size; /**< Size of isp blob */ 418 const uint8_t *isp_code; /**< ISP pointer to code */ 419 struct ia_css_acc_sp sp; /**< Standalone sp code */ 420 /**< Firmware handle between user space and kernel */ 421 uint32_t handle; 422 struct ia_css_data parameters; /**< Current SP parameters */ 423 }; 424 425 /** Firmware structure. 426 * This contains the header and actual blobs. 427 * For standalone, it contains SP and ISP blob. 428 * For a pipeline stage accelerator, it contains ISP code only. 429 * Since its members are variable size, their offsets are described in the 430 * header and computed using the access macros below. 431 */ 432 struct ia_css_acc_fw { 433 struct ia_css_acc_fw_hdr header; /**< firmware header */ 434 /* 435 int8_t isp_progname[]; **< ISP program name 436 int8_t sp_progname[]; **< SP program name, stand-alone only 437 uint8_t sp_code[]; **< SP blob, stand-alone only 438 uint8_t isp_code[]; **< ISP blob 439 */ 440 }; 441 442 /* Access macros for firmware */ 443 #define IA_CSS_ACC_OFFSET(t, f, n) ((t)((uint8_t *)(f)+(f->header.n))) 444 #define IA_CSS_ACC_SP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \ 445 sp.sp_prog_name_offset) 446 #define IA_CSS_ACC_ISP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \ 447 isp_prog_name_offset) 448 #define IA_CSS_ACC_SP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t *, f, \ 449 sp.sp_blob_offset) 450 #define IA_CSS_ACC_SP_DATA(f) (IA_CSS_ACC_SP_CODE(f) + \ 451 (f)->header.sp.fw.blob.data_source) 452 #define IA_CSS_ACC_ISP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t*, f,\ 453 isp_blob_offset) 454 #define IA_CSS_ACC_ISP_SIZE(f) ((f)->header.isp_size) 455 456 /* Binary name follows header immediately */ 457 #define IA_CSS_EXT_ISP_PROG_NAME(f) ((const char *)(f)+(f)->blob.prog_name_offset) 458 #define IA_CSS_EXT_ISP_MEM_OFFSETS(f) \ 459 ((const struct ia_css_memory_offsets *)((const char *)(f)+(f)->blob.mem_offsets)) 460 461 #endif /* !defined(__ISP) */ 462 463 enum ia_css_sp_sleep_mode { 464 SP_DISABLE_SLEEP_MODE = 0, 465 SP_SLEEP_AFTER_FRAME = 1 << 0, 466 SP_SLEEP_AFTER_IRQ = 1 << 1 467 }; 468 #endif /* _IA_CSS_ACC_TYPES_H */ 469