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Searched refs:m1 (Results 1 – 25 of 57) sorted by relevance

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/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_fw_defs.h17 (IRO[151].base + ((assertListEntry) * IRO[151].m1))
19 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
22 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
25 (IRO[163].base + ((funcId) * IRO[163].m1))
27 (IRO[153].base + ((funcId) * IRO[153].m1))
29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
31 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
35 (IRO[323].base + ((pfId) * IRO[323].m1))
37 (IRO[324].base + ((pfId) * IRO[324].m1))
39 (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
[all …]
Dbnx2x_init.h540 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \ argument
544 en_mask, {m1, m1h, m2, m3}, #block \
547 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \ argument
551 en_mask, {m1, m1h, m2, m3}, #block"_0" \
554 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \ argument
558 en_mask, {m1, m1h, m2, m3}, #block"_1" \
/drivers/clk/meson/
Dgxbb-aoclk-32k.c50 unsigned int m1; member
61 .m1 = 8,
88 unsigned long n2, m1, m2, f1, f2, p1, p2; in aoclk_cec_32k_recalc_rate() local
93 m1 = FIELD_GET(CLK_CNTL1_M1_MASK, reg1) + 1; in aoclk_cec_32k_recalc_rate()
99 p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2)); in aoclk_cec_32k_recalc_rate()
100 p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2)); in aoclk_cec_32k_recalc_rate()
163 reg = FIELD_PREP(CLK_CNTL1_M1_MASK, freq->m1 - 1); in aoclk_cec_32k_set_rate()
/drivers/video/fbdev/intelfb/
Dintelfbhw.c664 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, in calc_vclock() argument
670 m = (5 * (m1 + 2)) + (m2 + 2); in calc_vclock()
714 int i, m1, m2, n, p1, p2; in intelfbhw_print_hw_state() local
726 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
732 m1, m2, n, p1, p2); in intelfbhw_print_hw_state()
734 calc_vclock(index, m1, m2, n, p1, p2, 0)); in intelfbhw_print_hw_state()
737 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
742 m1, m2, n, p1, p2); in intelfbhw_print_hw_state()
744 calc_vclock(index, m1, m2, n, p1, p2, 0)); in intelfbhw_print_hw_state()
754 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
[all …]
/drivers/gpu/drm/gma500/
Dgma_display.c682 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in gma_pll_is_valid()
685 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
736 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in gma_find_best_pll()
738 (clock.m2 < clock.m1 || clock.m1 == 0) && in gma_find_best_pll()
Dcdv_intel_display.c50 .m1 = {.min = 0, .max = 0},
62 .m1 = {.min = 0, .max = 0},
77 .m1 = {.min = 0, .max = 0},
89 .m1 = {.min = 0, .max = 0},
101 .m1 = {.min = 0, .max = 0},
113 .m1 = {.min = 0, .max = 0},
424 clock.m1 = 0; in cdv_intel_find_dp_pll()
430 clock.m1 = 0; in cdv_intel_find_dp_pll()
440 clock.m1 = 0; in cdv_intel_find_dp_pll()
446 clock.m1 = 0; in cdv_intel_find_dp_pll()
[all …]
Dgma_display.h30 int m1, m2; member
49 struct gma_range_t dot, vco, n, m, m1, m2, p, p1; member
Dpsb_intel_display.c41 .m1 = {.min = 8, .max = 18},
53 .m1 = {.min = 8, .max = 18},
79 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
161 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; in psb_intel_crtc_mode_set()
341 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; in psb_intel_crtc_clock_get()
/drivers/gpu/drm/nouveau/dispnv04/
Darb.c60 int found, mclk_extra, mclk_loop, cbs, m1, p1; in nv04_calc_arb() local
96 m1 = clwm + cbs - 512; in nv04_calc_arb()
97 p1 = m1 * pclk_freq / mclk_freq; in nv04_calc_arb()
99 if ((p1 < m1 && m1 > 0) || clwm > 519) { in nv04_calc_arb()
/drivers/firmware/efi/
Dfake_mem.c43 const struct efi_mem_range *m1 = x1; in cmp_fake_mem() local
46 if (m1->range.start < m2->range.start) in cmp_fake_mem()
48 if (m1->range.start > m2->range.start) in cmp_fake_mem()
/drivers/ssb/
Dmain.c839 u32 n1, n2, clock, m1, m2, m3, mc; in ssb_calc_clock_rate() local
879 m1 = (m & SSB_CHIPCO_CLK_M1); in ssb_calc_clock_rate()
889 m1 = clkfactor_f6_resolve(m1); in ssb_calc_clock_rate()
901 return (clock / m1); in ssb_calc_clock_rate()
903 return (clock / (m1 * m2)); in ssb_calc_clock_rate()
905 return (clock / (m1 * m2 * m3)); in ssb_calc_clock_rate()
907 return (clock / (m1 * m3)); in ssb_calc_clock_rate()
911 m1 += SSB_CHIPCO_CLK_T2_BIAS; in ssb_calc_clock_rate()
914 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7))); in ssb_calc_clock_rate()
919 clock /= m1; in ssb_calc_clock_rate()
/drivers/pwm/
Dpwm-fsl-ftm.c186 enum fsl_pwm_clk m0, m1; in fsl_pwm_calculate_period() local
201 m1 = FSL_PWM_CLK_EXT; in fsl_pwm_calculate_period()
204 m1 = FSL_PWM_CLK_FIX; in fsl_pwm_calculate_period()
213 fpc->cnt_select = m1; in fsl_pwm_calculate_period()
215 return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1); in fsl_pwm_calculate_period()
/drivers/net/ethernet/apm/xgene-v2/
Dmain.c110 addr_hi = GET_BITS(NEXT_DESC_ADDRH, le64_to_cpu(raw_desc->m1)); in xge_refill_buffers()
111 addr_lo = GET_BITS(NEXT_DESC_ADDRL, le64_to_cpu(raw_desc->m1)); in xge_refill_buffers()
112 raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) | in xge_refill_buffers()
217 addr_hi = GET_BITS(NEXT_DESC_ADDRH, le64_to_cpu(raw_desc->m1)); in xge_start_xmit()
218 addr_lo = GET_BITS(NEXT_DESC_ADDRL, le64_to_cpu(raw_desc->m1)); in xge_start_xmit()
219 raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) | in xge_start_xmit()
Dring.c41 raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, next_dma) | in xge_setup_desc()
Dring.h69 __le64 m1; member
/drivers/net/wireless/intel/iwlegacy/
D4965.c688 const struct il_eeprom_calib_measure *m1; in il4965_interpolate_chan() local
709 m1 = &(il->calib_info->band_info[s].ch1. in il4965_interpolate_chan()
717 m1->actual_pow, ch_i2, in il4965_interpolate_chan()
721 m1->gain_idx, ch_i2, in il4965_interpolate_chan()
725 m1->temperature, in il4965_interpolate_chan()
730 m1->pa_det, ch_i2, in il4965_interpolate_chan()
734 m, m1->actual_pow, m2->actual_pow, in il4965_interpolate_chan()
737 m, m1->gain_idx, m2->gain_idx, in il4965_interpolate_chan()
740 m, m1->pa_det, m2->pa_det, omeas->pa_det); in il4965_interpolate_chan()
742 m, m1->temperature, m2->temperature, in il4965_interpolate_chan()
/drivers/usb/mon/
Dmon_main.c44 struct mon_bus *m1; in mon_reader_add() local
45 m1 = list_entry(p, struct mon_bus, bus_link); in mon_reader_add()
46 m1->u_bus->monitored = 1; in mon_reader_add()
/drivers/i2c/busses/
Di2c-sh7760.c395 unsigned long mck, m1, dff, odff, iclk; in calc_CCR() local
408 scgdm = cdfm = m1 = 0; in calc_CCR()
415 m1 = iclk / (20 + (scgd << 3)); in calc_CCR()
416 dff = abs(scl_hz - m1); in calc_CCR()
/drivers/media/common/saa7146/
Dsaa7146_video.c225 int i,p,m1,m2,m3,o1,o2; in saa7146_pgtable_build() local
230 m1 = ((size+PAGE_SIZE)/PAGE_SIZE)-1; in saa7146_pgtable_build()
236 size, m1, m2, m3, o1, o2); in saa7146_pgtable_build()
241 m1 = ((size+PAGE_SIZE)/PAGE_SIZE)-1; in saa7146_pgtable_build()
247 size, m1, m2, m3, o1, o2); in saa7146_pgtable_build()
280 for(i = m1; i <= m2 ; i++, ptr2++) { in saa7146_pgtable_build()
297 ptr1 = pt1->cpu+m1; in saa7146_pgtable_build()
298 fill = pt1->cpu[m1]; in saa7146_pgtable_build()
299 for(i=m1;i<1024;i++,ptr1++) { in saa7146_pgtable_build()
/drivers/media/pci/ttpci/
Dbudget-av.c476 u8 m1; in philips_su1278_ty_ci_set_symbol_rate() local
488 m1 = 0x14; in philips_su1278_ty_ci_set_symbol_rate()
490 m1 = 0x10; in philips_su1278_ty_ci_set_symbol_rate()
497 stv0299_writereg(fe, 0x0f, 0x80 | m1); in philips_su1278_ty_ci_set_symbol_rate()
849 u8 m1; in philips_sd1878_ci_set_symbol_rate() local
861 m1 = 0x14; in philips_sd1878_ci_set_symbol_rate()
863 m1 = 0x10; in philips_sd1878_ci_set_symbol_rate()
874 stv0299_writereg(fe, 0x0f, 0x80 | m1); in philips_sd1878_ci_set_symbol_rate()
/drivers/scsi/
Dmvumi.h405 int size, m1, m2; \
406 m1 = max(HSP_SIZE(1), HSP_SIZE(3)); \
408 size = max(m1, m2); \
/drivers/net/ethernet/neterion/vxge/
Dvxge-config.h848 #define VXGE_HW_DEVICE_TIM_INT_MASK_SET(m0, m1, i) { \ argument
854 m1[0] = 0x80000000; \
855 m1[1] = 0x40000000; \
859 #define VXGE_HW_DEVICE_TIM_INT_MASK_RESET(m0, m1, i) { \ argument
865 m1[0] = 0; \
866 m1[1] = 0; \
/drivers/net/ethernet/qlogic/qed/
Dqed_hsi.h2789 __le16 m1; member
3826 (IRO[1].base + ((port_id) * IRO[1].m1))
3829 (IRO[2].base + ((port_id) * IRO[2].m1))
3832 (IRO[3].base + ((vf_id) * IRO[3].m1))
3835 (IRO[4].base + (pf_id) * IRO[4].m1)
3838 (IRO[5].base + ((pf_id) * IRO[5].m1))
3841 (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
3844 (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
3847 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
3850 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
[all …]
/drivers/video/fbdev/nvidia/
Dnv_hw.c246 int found, mclk_extra, mclk_loop, cbs, m1, p1; in nv4CalcArbitration() local
341 m1 = clwm + cbs - 512; in nv4CalcArbitration()
342 p1 = m1 * pclk_freq / mclk_freq; in nv4CalcArbitration()
344 if ((p1 < m1) && (m1 > 0)) { in nv4CalcArbitration()
420 int found, mclk_extra, mclk_loop, cbs, m1; in nv10CalcArbitration() local
572 m1 = clwm + cbs - 1024; /* Amount of overfill */ in nv10CalcArbitration()
579 if ((p2 < m1) && (m1 > 0)) { in nv10CalcArbitration()
/drivers/net/ethernet/apm/xgene/
Dxgene_enet_hw.h336 __le64 m1; member
343 __le64 m1; member

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