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Searched refs:m2 (Results 1 – 25 of 46) sorted by relevance

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/drivers/clk/meson/
Dgxbb-aoclk-32k.c51 unsigned int m2; member
62 .m2 = 11,
88 unsigned long n2, m1, m2, f1, f2, p1, p2; in aoclk_cec_32k_recalc_rate() local
94 m2 = FIELD_GET(CLK_CNTL1_M2_MASK, reg1) + 1; in aoclk_cec_32k_recalc_rate()
99 p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2)); in aoclk_cec_32k_recalc_rate()
100 p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2)); in aoclk_cec_32k_recalc_rate()
165 reg |= FIELD_PREP(CLK_CNTL1_M2_MASK, freq->m2 - 1); in aoclk_cec_32k_set_rate()
/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_pll.c47 unsigned n, m, mf, m2, sd; in hdmi_pll_compute() local
63 m2 = DIV_ROUND_UP(min_dco, target_bitclk); in hdmi_pll_compute()
64 if (m2 == 0) in hdmi_pll_compute()
65 m2 = 1; in hdmi_pll_compute()
67 target_clkdco = target_bitclk * m2; in hdmi_pll_compute()
81 clkout = clkdco / m2; in hdmi_pll_compute()
87 n, m, mf, m2, sd); in hdmi_pll_compute()
93 pi->mX[0] = m2; in hdmi_pll_compute()
/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_fw_defs.h20 IRO[157].m2))
23 IRO[158].m2))
29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
32 * IRO[142].m2) + ((sbId) * IRO[142].m3))
39 (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
41 (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
43 (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
45 (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
47 (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
49 (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
[all …]
Dbnx2x_init.h540 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \ argument
544 en_mask, {m1, m1h, m2, m3}, #block \
547 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \ argument
551 en_mask, {m1, m1h, m2, m3}, #block"_0" \
554 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \ argument
558 en_mask, {m1, m1h, m2, m3}, #block"_1" \
/drivers/video/fbdev/intelfb/
Dintelfbhw.c664 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, in calc_vclock() argument
670 m = (5 * (m1 + 2)) + (m2 + 2); in calc_vclock()
714 int i, m1, m2, n, p1, p2; in intelfbhw_print_hw_state() local
727 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
732 m1, m2, n, p1, p2); in intelfbhw_print_hw_state()
734 calc_vclock(index, m1, m2, n, p1, p2, 0)); in intelfbhw_print_hw_state()
738 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
742 m1, m2, n, p1, p2); in intelfbhw_print_hw_state()
744 calc_vclock(index, m1, m2, n, p1, p2, 0)); in intelfbhw_print_hw_state()
755 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
[all …]
/drivers/gpu/drm/gma500/
Dcdv_intel_display.c51 .m2 = {.min = 58, .max = 158},
63 .m2 = {.min = 58, .max = 158},
78 .m2 = {.min = 65, .max = 130},
90 .m2 = {.min = 58, .max = 158},
102 .m2 = {.min = 65, .max = 130},
114 .m2 = {.min = 58, .max = 162},
281 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
404 clock->m = clock->m2 + 2; in cdv_intel_clock()
425 clock.m2 = 118; in cdv_intel_find_dp_pll()
431 clock.m2 = 98; in cdv_intel_find_dp_pll()
[all …]
Dgma_display.c680 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in gma_pll_is_valid()
685 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
737 for (clock.m2 = limit->m2.min; in gma_find_best_pll()
738 (clock.m2 < clock.m1 || clock.m1 == 0) && in gma_find_best_pll()
739 clock.m2 <= limit->m2.max; clock.m2++) { in gma_find_best_pll()
Dgma_display.h30 int m1, m2; member
49 struct gma_range_t dot, vco, n, m, m1, m2, p, p1; member
Dpsb_intel_display.c42 .m2 = {.min = 3, .max = 7},
54 .m2 = {.min = 3, .max = 7},
79 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
161 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; in psb_intel_crtc_mode_set()
342 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; in psb_intel_crtc_clock_get()
/drivers/gpu/drm/omapdrm/dss/
Dpll.c280 unsigned n, m, mf, m2, sd; in dss_pll_calc_b() local
291 m2 = DIV_ROUND_UP(min_dco, target_clkout); in dss_pll_calc_b()
292 if (m2 == 0) in dss_pll_calc_b()
293 m2 = 1; in dss_pll_calc_b()
295 target_clkdco = target_clkout * m2; in dss_pll_calc_b()
309 clkout = clkdco / m2; in dss_pll_calc_b()
315 n, m, mf, m2, sd); in dss_pll_calc_b()
321 cinfo->mX[0] = m2; in dss_pll_calc_b()
/drivers/firmware/efi/
Dfake_mem.c44 const struct efi_mem_range *m2 = x2; in cmp_fake_mem() local
46 if (m1->range.start < m2->range.start) in cmp_fake_mem()
48 if (m1->range.start > m2->range.start) in cmp_fake_mem()
/drivers/ssb/
Dmain.c839 u32 n1, n2, clock, m1, m2, m3, mc; in ssb_calc_clock_rate() local
880 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); in ssb_calc_clock_rate()
892 m2 += SSB_CHIPCO_CLK_F5_BIAS; in ssb_calc_clock_rate()
894 m2 = clkfactor_f6_resolve(m2); in ssb_calc_clock_rate()
903 return (clock / (m1 * m2)); in ssb_calc_clock_rate()
905 return (clock / (m1 * m2 * m3)); in ssb_calc_clock_rate()
912 m2 += SSB_CHIPCO_CLK_T2M2_BIAS; in ssb_calc_clock_rate()
915 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10))); in ssb_calc_clock_rate()
921 clock /= m2; in ssb_calc_clock_rate()
/drivers/media/usb/zr364xx/
Dzr364xx.c280 static message m2[] = { variable
293 static message *init[4] = { m0, m1, m2, m2 };
881 m2[1].value = 0xf000 + mode; in zr364xx_vidioc_s_fmt_vid_cap()
887 m2[1].value = 0xf000 + 4; in zr364xx_vidioc_s_fmt_vid_cap()
890 m2[1].value = 0xf000 + 0; in zr364xx_vidioc_s_fmt_vid_cap()
893 m2[1].value = 0xf000 + 1; in zr364xx_vidioc_s_fmt_vid_cap()
1480 m2[1].value = 0xf000 + mode; in zr364xx_probe()
1486 m2[1].value = 0xf000 + 4; in zr364xx_probe()
1489 m2[1].value = 0xf000 + 0; in zr364xx_probe()
1492 m2[1].value = 0xf000 + 1; in zr364xx_probe()
/drivers/ata/
Dahci_imx.c283 int m1, m2, a; in sata_ahci_read_temperature() local
340 m2 = read_adc_sum(dev, rtune_ctl_reg, mmio); in sata_ahci_read_temperature()
360 if (!(m2 / 1000)) in sata_ahci_read_temperature()
361 m2 = 1000; in sata_ahci_read_temperature()
362 a = (m2 - m1) / (m2/1000); in sata_ahci_read_temperature()
Dsata_mv.c3364 u32 m2, m3; in mv6_phy_errata() local
3367 m2 = readl(port_mmio + PHY_MODE2); in mv6_phy_errata()
3368 m2 &= ~(1 << 16); in mv6_phy_errata()
3369 m2 |= (1 << 31); in mv6_phy_errata()
3370 writel(m2, port_mmio + PHY_MODE2); in mv6_phy_errata()
3374 m2 = readl(port_mmio + PHY_MODE2); in mv6_phy_errata()
3375 m2 &= ~((1 << 16) | (1 << 31)); in mv6_phy_errata()
3376 writel(m2, port_mmio + PHY_MODE2); in mv6_phy_errata()
3414 m2 = readl(port_mmio + PHY_MODE2); in mv6_phy_errata()
3416 m2 &= ~MV_M2_PREAMP_MASK; in mv6_phy_errata()
[all …]
/drivers/net/wireless/intel/iwlegacy/
D4965.c689 const struct il_eeprom_calib_measure *m2; in il4965_interpolate_chan() local
711 m2 = &(il->calib_info->band_info[s].ch2. in il4965_interpolate_chan()
718 m2->actual_pow); in il4965_interpolate_chan()
722 m2->gain_idx); in il4965_interpolate_chan()
727 m2->temperature); in il4965_interpolate_chan()
731 m2->pa_det); in il4965_interpolate_chan()
734 m, m1->actual_pow, m2->actual_pow, in il4965_interpolate_chan()
737 m, m1->gain_idx, m2->gain_idx, in il4965_interpolate_chan()
740 m, m1->pa_det, m2->pa_det, omeas->pa_det); in il4965_interpolate_chan()
742 m, m1->temperature, m2->temperature, in il4965_interpolate_chan()
/drivers/scsi/
Dmvumi.h405 int size, m1, m2; \
407 m2 = max(HSP_SIZE(2), HSP_SIZE(4)); \
408 size = max(m1, m2); \
/drivers/input/touchscreen/
Dmxs-lradc-ts.c237 unsigned int pressure, m1, m2; in mxs_lradc_read_ts_pressure() local
248 m2 = mxs_lradc_ts_read_raw_channel(ts, ch2); in mxs_lradc_read_ts_pressure()
250 if (m2 == 0) { in mxs_lradc_read_ts_pressure()
258 pressure /= m2; in mxs_lradc_read_ts_pressure()
/drivers/gpu/drm/i915/
Dintel_display.c154 } dot, vco, n, m, m1, m2, p, p1; member
234 .m2 = { .min = 6, .max = 16 },
247 .m2 = { .min = 6, .max = 16 },
260 .m2 = { .min = 6, .max = 16 },
273 .m2 = { .min = 3, .max = 7 },
286 .m2 = { .min = 3, .max = 7 },
300 .m2 = { .min = 5, .max = 11 },
315 .m2 = { .min = 5, .max = 11 },
328 .m2 = { .min = 5, .max = 11 },
342 .m2 = { .min = 5, .max = 11 },
[all …]
Dintel_dp.c59 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
61 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
66 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
68 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
73 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
75 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
89 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
91 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
93 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
1623 struct drm_display_mode *m2) in intel_edp_compare_alt_mode() argument
[all …]
/drivers/media/common/saa7146/
Dsaa7146_video.c225 int i,p,m1,m2,m3,o1,o2; in saa7146_pgtable_build() local
231 m2 = ((size+(size/4)+PAGE_SIZE)/PAGE_SIZE)-1; in saa7146_pgtable_build()
236 size, m1, m2, m3, o1, o2); in saa7146_pgtable_build()
242 m2 = ((size+(size/2)+PAGE_SIZE)/PAGE_SIZE)-1; in saa7146_pgtable_build()
247 size, m1, m2, m3, o1, o2); in saa7146_pgtable_build()
280 for(i = m1; i <= m2 ; i++, ptr2++) { in saa7146_pgtable_build()
289 for(i = m2; i <= m3; i++,ptr3++) { in saa7146_pgtable_build()
/drivers/net/ethernet/apm/xgene-v2/
Dring.h70 __le64 m2; member
/drivers/video/fbdev/matrox/
Dmatroxfb_base.c587 unsigned int m2 = PAGE_SIZE; /* or 128 if you do not need PAGE ALIGNED address */ in matroxfb_decode_var() local
591 while (m2 >= m1) m2 -= m1; in matroxfb_decode_var()
592 swap(m1, m2); in matroxfb_decode_var()
594 m2 = linelen * PAGE_SIZE / m2; in matroxfb_decode_var()
595 *ydstorg = m2 = 0x400000 % m2; in matroxfb_decode_var()
596 max_yres = (vramlen - m2) / linelen; in matroxfb_decode_var()
/drivers/video/fbdev/
Dsstfb.c292 int m, m2, n, p, best_err, fout; in sst_calc_pll() local
305 m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ; in sst_calc_pll()
307 m = (m2 % 2 ) ? m2/2+1 : m2/2 ; in sst_calc_pll()
/drivers/dma/
Dxgene-dma.c213 __le64 m2; member
404 return &desc->m2; in xgene_dma_lookup_ext8()
440 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT); in xgene_dma_prep_xor_desc()
447 desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt)); in xgene_dma_prep_xor_desc()
455 desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8))); in xgene_dma_prep_xor_desc()

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