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Searched refs:max_lane (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/msm/edp/
Dedp_phy.c76 void msm_edp_phy_lane_power_ctrl(struct edp_phy *phy, bool up, u32 max_lane) in msm_edp_phy_lane_power_ctrl() argument
86 for (i = 0; i < max_lane; i++) in msm_edp_phy_lane_power_ctrl()
91 for (i = max_lane; i < EDP_MAX_LANE; i++) in msm_edp_phy_lane_power_ctrl()
Dedp.h67 void msm_edp_phy_lane_power_ctrl(struct edp_phy *phy, bool up, u32 max_lane);
Dedp_ctrl.c414 u8 max_lane = ctrl->dp_link.num_lanes; in edp_fill_link_cfg() local
433 for (lane = 1; lane <= max_lane; lane <<= 1) { in edp_fill_link_cfg()
707 u8 rate, lane, max_lane; in edp_link_rate_down_shift() local
712 max_lane = ctrl->dp_link.num_lanes; in edp_link_rate_down_shift()
725 if (lane >= 1 && lane < max_lane) in edp_link_rate_down_shift()
/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c636 enum link_lane_count_type max_lane, in analogix_dp_init_training() argument
664 if (dp->link_train.lane_count > max_lane) in analogix_dp_init_training()
665 dp->link_train.lane_count = max_lane; in analogix_dp_init_training()