Searched refs:mscr (Results 1 – 3 of 3) sorted by relevance
/drivers/net/phy/ |
D | marvell.c | 465 int err, oldpage, mscr; in m88e1121_config_aneg_rgmii_delays() local 471 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG); in m88e1121_config_aneg_rgmii_delays() 472 if (mscr < 0) { in m88e1121_config_aneg_rgmii_delays() 473 err = mscr; in m88e1121_config_aneg_rgmii_delays() 477 mscr &= MII_88E1121_PHY_MSCR_DELAY_MASK; in m88e1121_config_aneg_rgmii_delays() 480 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY | in m88e1121_config_aneg_rgmii_delays() 483 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY; in m88e1121_config_aneg_rgmii_delays() 485 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY; in m88e1121_config_aneg_rgmii_delays() 487 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr); in m88e1121_config_aneg_rgmii_delays() 518 int err, oldpage, mscr; in m88e1318_config_aneg() local [all …]
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/drivers/edac/ |
D | cpc925_edac.c | 895 u32 mscr; in cpc925_get_sdram_scrub_rate() local 898 mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET); in cpc925_get_sdram_scrub_rate() 899 si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT; in cpc925_get_sdram_scrub_rate() 901 edac_dbg(0, "Mem Scrub Ctrl Register 0x%x\n", mscr); in cpc925_get_sdram_scrub_rate() 903 if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) || in cpc925_get_sdram_scrub_rate()
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/drivers/net/ethernet/dlink/ |
D | dl2k.c | 1506 __u16 mscr; in mii_get_media() local 1522 mscr = mii_read (dev, phy_addr, MII_CTRL1000); in mii_get_media() 1524 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) { in mii_get_media() 1528 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) { in mii_get_media() 1666 mscr = mii_read (dev, phy_addr, MII_CTRL1000); in mii_set_media() 1667 mscr |= MII_MSCR_CFG_ENABLE; in mii_set_media() 1668 mscr &= ~MII_MSCR_CFG_VALUE = 0; in mii_set_media()
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