Searched refs:pipestat (Results 1 – 5 of 5) sorted by relevance
91 u32 pipestat = I915_READ(reg) & 0xffff0000; in i9xx_check_fifo_underruns() local95 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()98 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()111 u32 pipestat = I915_READ(reg) & 0xffff0000; in i9xx_set_fifo_underrun_reporting() local116 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_set_fifo_underrun_reporting()119 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
542 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; in __i915_enable_pipestat() local553 if ((pipestat & enable_mask) == enable_mask) in __i915_enable_pipestat()559 pipestat |= enable_mask | status_mask; in __i915_enable_pipestat()560 I915_WRITE(reg, pipestat); in __i915_enable_pipestat()569 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; in __i915_disable_pipestat() local580 if ((pipestat & enable_mask) == 0) in __i915_disable_pipestat()585 pipestat &= ~enable_mask; in __i915_disable_pipestat()586 I915_WRITE(reg, pipestat); in __i915_disable_pipestat()
88 if ((dev_priv->pipestat[pipe] & mask) != mask) { in psb_enable_pipestat()90 dev_priv->pipestat[pipe] |= mask; in psb_enable_pipestat()105 if ((dev_priv->pipestat[pipe] & mask) != 0) { in psb_disable_pipestat()107 dev_priv->pipestat[pipe] &= ~mask; in psb_disable_pipestat()131 if (dev_priv->pipestat[pipe] == 0) { in mid_disable_pipe_event()153 uint32_t pipe_enable = dev_priv->pipestat[pipe]; in mid_pipe_event_handler()154 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16; in mid_pipe_event_handler()
364 dev_priv->pipestat[0] = 0; in psb_driver_load()365 dev_priv->pipestat[1] = 0; in psb_driver_load()366 dev_priv->pipestat[2] = 0; in psb_driver_load()
482 uint32_t pipestat[PSB_NUM_PIPE]; member