| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
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| /drivers/gpu/drm/hisilicon/hibmc/ |
| D | hibmc_drm_de.c | 285 u32 *pll1, u32 *pll2) in get_pll_config() argument
293 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
300 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
316 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
325 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.c | 132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
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| /drivers/gpu/drm/tegra/ |
| D | hdmi.c | 34 u32 pll1; member
189 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
204 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
222 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
236 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
250 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
267 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
285 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
304 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
323 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
[all …]
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| /drivers/clk/sirf/ |
| D | clk-prima2.c | 61 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
136 for (i = pll1; i < maxclk; i++) { in prima2_clk_init()
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| D | clk-atlas6.c | 62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
137 for (i = pll1; i < maxclk; i++) { in atlas6_clk_init()
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| /drivers/clk/mxs/ |
| D | clk-imx28.c | 139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
175 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
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| /drivers/gpu/drm/i915/ |
| D | intel_dpll_mgr.h | 136 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, member
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| D | intel_dpll_mgr.c | 1474 temp |= pll->state.hw_state.pll1; in bxt_ddi_pll_enable()
1601 hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
1602 hw_state->pll1 &= PORT_PLL_N_MASK; in bxt_ddi_pll_get_hw_state()
1757 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n); in bxt_ddi_set_dpll_hw_state()
1859 hw_state->pll1, in bxt_dump_hw_state()
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| D | intel_ddi.c | 1352 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; in bxt_calc_pll_link()
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