| /drivers/clk/rockchip/ |
| D | clk-pll.c | 149 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
171 do_div(rate64, cur.refdiv); in rockchip_rk3036_pll_recalc_rate()
177 do_div(frac_rate64, cur.refdiv); in rockchip_rk3036_pll_recalc_rate()
199 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
218 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
316 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
319 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
323 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
622 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) in rockchip_rk3399_pll_get_params()
648 do_div(rate64, cur.refdiv); in rockchip_rk3399_pll_recalc_rate()
[all …]
|
| D | clk.h | 161 .refdiv = _refdiv, \
210 unsigned int refdiv; member
|
| /drivers/clk/pistachio/ |
| D | clk-pll.c | 209 if (!params || !params->refdiv) in pll_gf40lp_frac_set_rate()
215 vco = div64_u64(vco, params->refdiv << 24); in pll_gf40lp_frac_set_rate()
221 val = div64_u64(params->fref, params->refdiv); in pll_gf40lp_frac_set_rate()
232 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | in pll_gf40lp_frac_set_rate()
366 if (!params || !params->refdiv) in pll_gf40lp_laint_set_rate()
369 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
374 val = div_u64(params->fref, params->refdiv); in pll_gf40lp_laint_set_rate()
400 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | in pll_gf40lp_laint_set_rate()
|
| D | clk.h | 100 unsigned long long refdiv; member
|
| /drivers/net/wireless/ath/ath10k/ |
| D | hw.c | 487 .refdiv = 0,
495 .refdiv = 0,
503 .refdiv = 0,
511 .refdiv = 0,
519 .refdiv = 0,
527 .refdiv = 0,
535 .refdiv = 0,
543 .refdiv = 0,
815 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | in ath10k_hw_qca6174_enable_pll_clock()
|
| D | hw.h | 483 u32 refdiv; member
|
| /drivers/clk/berlin/ |
| D | berlin2-avpll.c | 170 u32 reg, refdiv, fbdiv; in berlin2_avpll_vco_recalc_rate() local
175 refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT; in berlin2_avpll_vco_recalc_rate()
176 refdiv = vco_refdiv[refdiv]; in berlin2_avpll_vco_recalc_rate()
179 do_div(freq, refdiv); in berlin2_avpll_vco_recalc_rate()
|
| /drivers/media/dvb-frontends/ |
| D | cx24113.c | 95 u8 refdiv; member
291 static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv) in cx24113_set_ref_div() argument
294 refdiv = 2; in cx24113_set_ref_div()
295 return state->refdiv = refdiv; in cx24113_set_ref_div()
406 cx24113_set_nfr(state, n, f, state->refdiv); in cx24113_set_frequency()
|
| /drivers/clk/ |
| D | clk-axm5516.c | 55 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
61 refdiv = ((control >> 16) & 0x1f) + 1; in axxia_pllclk_recalc()
62 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
|
| /drivers/net/wireless/ath/ath9k/ |
| D | hw.c | 832 u32 regval, pll2_divint, pll2_divfrac, refdiv; in ath9k_hw_init_pll() local
845 refdiv = 1; in ath9k_hw_init_pll()
849 refdiv = 3; in ath9k_hw_init_pll()
855 refdiv = 5; in ath9k_hw_init_pll()
861 refdiv = 1; in ath9k_hw_init_pll()
873 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_mode.h | 351 uint8_t refdiv; member
|
| D | atombios_crtc.c | 340 if (amdgpu_crtc->ss.refdiv) { in amdgpu_atombios_crtc_adjust_pll()
342 amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv; in amdgpu_atombios_crtc_adjust_pll()
|
| /drivers/gpu/drm/radeon/ |
| D | radeon_mode.h | 316 uint8_t refdiv; member
|
| D | atombios_crtc.c | 627 if (radeon_crtc->ss.refdiv) { in atombios_adjust_pll()
629 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; in atombios_adjust_pll()
|
| D | radeon_atombios.c | 1417 ss->refdiv = ss_assign->ucRecommendedRef_Div; in radeon_atombios_get_ppll_ss_info()
|