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Searched refs:rf3wireOffset (Results 1 – 9 of 9) sorted by relevance

/drivers/staging/rtl8192u/
Dr819xU_phy.c149 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, in rtl8192_phy_RFSerialRead()
158 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, in rtl8192_phy_RFSerialRead()
190 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, in rtl8192_phy_RFSerialRead()
230 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, in rtl8192_phy_RFSerialWrite()
237 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, in rtl8192_phy_RFSerialWrite()
254 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); in rtl8192_phy_RFSerialWrite()
264 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, in rtl8192_phy_RFSerialWrite()
605 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; in rtl8192_InitBBRFRegDef()
606 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in rtl8192_InitBBRFRegDef()
607 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; in rtl8192_InitBBRFRegDef()
[all …]
Dr8192U.h670 u32 rf3wireOffset; member
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phy.c115 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, in _rtl92e_phy_rf_read()
122 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, in _rtl92e_phy_rf_read()
147 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, in _rtl92e_phy_rf_read()
172 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, in _rtl92e_phy_rf_write()
179 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, in _rtl92e_phy_rf_write()
193 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); in _rtl92e_phy_rf_write()
201 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, in _rtl92e_phy_rf_write()
414 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; in _rtl92e_init_bb_rf_reg_def()
415 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in _rtl92e_init_bb_rf_reg_def()
416 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; in _rtl92e_init_bb_rf_reg_def()
[all …]
Dr8190P_def.h119 u32 rf3wireOffset; member
/drivers/staging/rtl8188eu/hal/
Dbb_cfg.c604 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter; in rtl88e_phy_init_bb_rf_register_definition()
605 reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter; in rtl88e_phy_init_bb_rf_register_definition()
Dphy.c115 phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr); in rf_serial_write()
/drivers/staging/rtl8188eu/include/
DHal8188EPhyCfg.h111 u32 rf3wireOffset; /* LSSI data: */ member
/drivers/staging/rtl8723bs/hal/
Drtl8723b_phycfg.c266 PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); in phy_RFSerialWrite_8723B()
424 pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ in phy_InitBBRFRegisterDefinition()
425 pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in phy_InitBBRFRegisterDefinition()
/drivers/staging/rtl8723bs/include/
Dhal_com_phycfg.h66 u32 rf3wireOffset; /* LSSI data: */ member