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Searched refs:save (Results 1 – 25 of 100) sorted by relevance

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/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dagp.c60 u32 save[2]; in nvkm_agp_preinit() local
72 save[0] = nvkm_pci_rd32(pci, 0x0004); in nvkm_agp_preinit()
73 nvkm_pci_wr32(pci, 0x0004, save[0] & ~0x00000004); in nvkm_agp_preinit()
77 save[1] = nvkm_mask(device, 0x000200, 0x00011100, 0x00000000); in nvkm_agp_preinit()
78 nvkm_mask(device, 0x000200, 0x00011100, save[1]); in nvkm_agp_preinit()
81 nvkm_pci_wr32(pci, 0x0004, save[0]); in nvkm_agp_preinit()
/drivers/pci/
Dvc.c28 u32 *buf, int dwords, bool save) in pci_vc_save_restore_dwords() argument
33 if (save) in pci_vc_save_restore_dwords()
188 bool save) in pci_vc_do_save_buffer() argument
197 pci_vc_do_save_buffer(dev, pos, NULL, save)) { in pci_vc_do_save_buffer()
218 if (save) in pci_vc_do_save_buffer()
256 size / 4, save); in pci_vc_do_save_buffer()
261 if (!save) in pci_vc_do_save_buffer()
303 size / 4, save); in pci_vc_do_save_buffer()
313 if (save) in pci_vc_do_save_buffer()
/drivers/pinctrl/samsung/
Dpinctrl-exynos.c555 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_suspend_bank() local
558 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET in exynos_pinctrl_suspend_bank()
560 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_suspend_bank()
562 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_suspend_bank()
565 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); in exynos_pinctrl_suspend_bank()
566 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); in exynos_pinctrl_suspend_bank()
567 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); in exynos_pinctrl_suspend_bank()
584 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_resume_bank() local
589 + bank->eint_offset), save->eint_con); in exynos_pinctrl_resume_bank()
592 + 2 * bank->eint_offset), save->eint_fltcon0); in exynos_pinctrl_resume_bank()
[all …]
/drivers/iio/dac/
Dm62332.c38 u8 save[M62332_CHANNELS]; member
144 data->save[0] = data->raw[0]; in m62332_suspend()
145 data->save[1] = data->raw[1]; in m62332_suspend()
161 ret = m62332_set_value(indio_dev, data->save[0], 0); in m62332_resume()
165 return m62332_set_value(indio_dev, data->save[1], 1); in m62332_resume()
/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramgp100.c58 u32 save = nvkm_rd32(device, 0x9a065c) & 0x000000f0; in gp100_ram_init() local
60 if (i != save >> 4) { in gp100_ram_init()
65 nvkm_mask(device, 0x9a065c, 0x000000f0, save); in gp100_ram_init()
/drivers/video/fbdev/aty/
Dradeon_base.c306 u32 save, tmp; in radeon_pll_errata_after_data_slow() local
307 save = INREG(CLOCK_CNTL_INDEX); in radeon_pll_errata_after_data_slow()
308 tmp = save & ~(0x3f | PLL_WR_EN); in radeon_pll_errata_after_data_slow()
311 OUTREG(CLOCK_CNTL_INDEX, save); in radeon_pll_errata_after_data_slow()
1324 struct radeon_regs *save) in radeon_save_state() argument
1327 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); in radeon_save_state()
1328 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); in radeon_save_state()
1329 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); in radeon_save_state()
1330 save->dac_cntl = INREG(DAC_CNTL); in radeon_save_state()
1331 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); in radeon_save_state()
[all …]
/drivers/misc/sgi-gru/
Dgrumain.c492 static void gru_load_context_data(void *save, void *grubase, int ctxnum, in gru_load_context_data() argument
508 save += gru_copy_handle(cb, save); in gru_load_context_data()
509 save += gru_copy_handle(cbe + i * GRU_HANDLE_STRIDE, in gru_load_context_data()
510 save); in gru_load_context_data()
523 memcpy(gseg + GRU_DS_BASE, save, length); in gru_load_context_data()
528 static void gru_unload_context_data(void *save, void *grubase, int ctxnum, in gru_unload_context_data() argument
548 save += gru_copy_handle(save, cb); in gru_unload_context_data()
549 save += gru_copy_handle(save, cbe + i * GRU_HANDLE_STRIDE); in gru_unload_context_data()
552 memcpy(save, gseg + GRU_DS_BASE, length); in gru_unload_context_data()
/drivers/mfd/
Dsm501.c259 unsigned long save; in sm501_misc_control() local
262 spin_lock_irqsave(&sm->reg_lock, save); in sm501_misc_control()
274 spin_unlock_irqrestore(&sm->reg_lock, save); in sm501_misc_control()
293 unsigned long save; in sm501_modify_reg() local
295 spin_lock_irqsave(&sm->reg_lock, save); in sm501_modify_reg()
304 spin_unlock_irqrestore(&sm->reg_lock, save); in sm501_modify_reg()
926 unsigned long save; in sm501_gpio_set() local
932 spin_lock_irqsave(&smgpio->lock, save); in sm501_gpio_set()
942 spin_unlock_irqrestore(&smgpio->lock, save); in sm501_gpio_set()
951 unsigned long save; in sm501_gpio_input() local
[all …]
/drivers/spi/
Dspidev.c404 u32 save = spi->mode; in spidev_ioctl() local
415 spi->mode = save; in spidev_ioctl()
423 u32 save = spi->mode; in spidev_ioctl() local
431 spi->mode = save; in spidev_ioctl()
440 u8 save = spi->bits_per_word; in spidev_ioctl() local
445 spi->bits_per_word = save; in spidev_ioctl()
453 u32 save = spi->max_speed_hz; in spidev_ioctl() local
461 spi->max_speed_hz = save; in spidev_ioctl()
/drivers/gpu/drm/radeon/
Drv515.c293 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) in rv515_mc_stop() argument
298 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); in rv515_mc_stop()
299 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); in rv515_mc_stop()
307 save->crtc_enabled[i] = true; in rv515_mc_stop()
330 save->crtc_enabled[i] = false; in rv515_mc_stop()
333 save->crtc_enabled[i] = false; in rv515_mc_stop()
360 if (save->crtc_enabled[i]) { in rv515_mc_stop()
375 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) in rv515_mc_resume() argument
404 if (save->crtc_enabled[i]) { in rv515_mc_resume()
446 if (save->crtc_enabled[i]) { in rv515_mc_resume()
[all …]
Dr520.c135 struct rv515_mc_save save; in r520_mc_program() local
138 rv515_mc_stop(rdev, &save); in r520_mc_program()
164 rv515_mc_resume(rdev, &save); in r520_mc_program()
Dr100.c2552 struct r100_mc_save save; in r100_asic_reset() local
2560 r100_mc_stop(rdev, &save); in r100_asic_reset()
2602 r100_mc_resume(rdev, &save); in r100_asic_reset()
2864 uint32_t save, tmp; in r100_pll_errata_after_data() local
2866 save = RREG32(RADEON_CLOCK_CNTL_INDEX); in r100_pll_errata_after_data()
2867 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); in r100_pll_errata_after_data()
2870 WREG32(RADEON_CLOCK_CNTL_INDEX, save); in r100_pll_errata_after_data()
3765 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) in r100_mc_stop() argument
3774 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); in r100_mc_stop()
3775 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); in r100_mc_stop()
[all …]
Drs600.c453 struct rv515_mc_save save; in rs600_asic_reset() local
462 rv515_mc_stop(rdev, &save); in rs600_asic_reset()
509 rv515_mc_resume(rdev, &save); in rs600_asic_reset()
957 struct rv515_mc_save save; in rs600_mc_program() local
960 rv515_mc_stop(rdev, &save); in rs600_mc_program()
977 rv515_mc_resume(rdev, &save); in rs600_mc_program()
Drs400.c390 struct r100_mc_save save; in rs400_mc_program() local
393 r100_mc_stop(rdev, &save); in rs400_mc_program()
402 r100_mc_resume(rdev, &save); in rs400_mc_program()
/drivers/gpu/drm/vmwgfx/
Dvmwgfx_kms.c1763 struct vmw_vga_topology_state *save; in vmw_kms_save_vga() local
1786 save = &vmw_priv->vga_save[i]; in vmw_kms_save_vga()
1788 save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY); in vmw_kms_save_vga()
1789 save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X); in vmw_kms_save_vga()
1790 save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y); in vmw_kms_save_vga()
1791 save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH); in vmw_kms_save_vga()
1792 save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT); in vmw_kms_save_vga()
1795 save->width == 0 && save->height == 0) { in vmw_kms_save_vga()
1802 save->width = vmw_priv->vga_width - save->pos_x; in vmw_kms_save_vga()
1803 save->height = vmw_priv->vga_height - save->pos_y; in vmw_kms_save_vga()
[all …]
/drivers/gpu/drm/amd/amdgpu/
Dcik.c1069 struct kv_reset_save_regs *save) in kv_save_regs_for_reset() argument
1071 save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE); in kv_save_regs_for_reset()
1072 save->gmcon_misc = RREG32(mmGMCON_MISC); in kv_save_regs_for_reset()
1073 save->gmcon_misc3 = RREG32(mmGMCON_MISC3); in kv_save_regs_for_reset()
1075 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute & in kv_save_regs_for_reset()
1077 WREG32(mmGMCON_MISC, save->gmcon_misc & in kv_save_regs_for_reset()
1083 struct kv_reset_save_regs *save) in kv_restore_regs_for_reset() argument
1150 WREG32(mmGMCON_MISC3, save->gmcon_misc3); in kv_restore_regs_for_reset()
1151 WREG32(mmGMCON_MISC, save->gmcon_misc); in kv_restore_regs_for_reset()
1152 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); in kv_restore_regs_for_reset()
/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dchang84.c97 u32 engn, save; in g84_fifo_chan_engine_fini() local
106 save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); in g84_fifo_chan_engine_fini()
112 nvkm_wr32(device, 0x002520, save); in g84_fifo_chan_engine_fini()
/drivers/net/wireless/broadcom/b43/
Dphy_lcn.c64 u16 save[2]; in b43_radio_2064_channel_setup() local
79 save[0] = b43_radio_read(dev, 0x044); in b43_radio_2064_channel_setup()
80 save[1] = b43_radio_read(dev, 0x12b); in b43_radio_2064_channel_setup()
98 b43_radio_write(dev, 0x044, save[0]); in b43_radio_2064_channel_setup()
99 b43_radio_write(dev, 0x12b, save[1]); in b43_radio_2064_channel_setup()
/drivers/gpu/drm/nouveau/dispnv04/
Ddisp.c115 crtc->save(&crtc->base); in nv04_display_create()
163 crtc->save(&crtc->base); in nv04_display_init()
/drivers/media/pci/bt8xx/
Dbttv-gpio.c111 struct bttv_sub_device *sub, *save; in bttv_sub_del_devices() local
113 list_for_each_entry_safe(sub, save, &core->subs, list) { in bttv_sub_del_devices()
/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
Dgpc.fuc285 // save context size, and tell HUB we're done
398 // $p1 clear on save, set on load
400 // on save it means: "a load will follow this save"
401 // on load it means: "a save preceeded this load"
477 // if load, or a save without a load following, do some
/drivers/video/logo/
Dlogo_blackfin_clut224.ppm3 # gimp linux_bf.svg (create 80x80 save as linux_bf.ppm)
Dlogo_blackfin_vga16.ppm3 # gimp linux_bf.svg (create 80x80 save as linux_bf.ppm)
/drivers/gpu/drm/nouveau/
Dnouveau_crtc.h67 void (*save)(struct drm_crtc *crtc); member
/drivers/hwmon/
Dw83781d.c1850 int val, save, found = 0; in w83781d_isa_found() local
1883 save = inb_p(address + W83781D_ADDR_REG_OFFSET); in w83781d_isa_found()
1884 if (save & 0x80) { in w83781d_isa_found()
1888 val = ~save & 0x7f; in w83781d_isa_found()
1891 outb_p(save, address + W83781D_ADDR_REG_OFFSET); in w83781d_isa_found()
1904 save = inb_p(address + W83781D_DATA_REG_OFFSET); in w83781d_isa_found()
1907 if ((!(save & 0x80) && (val != 0xa3)) in w83781d_isa_found()
1908 || ((save & 0x80) && (val != 0x5c))) { in w83781d_isa_found()
1927 save = inb_p(address + W83781D_DATA_REG_OFFSET); in w83781d_isa_found()
1928 outb_p(save & 0xf8, address + W83781D_DATA_REG_OFFSET); in w83781d_isa_found()

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