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Searched refs:timings (Results 1 – 25 of 131) sorted by relevance

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/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_wp.c146 struct omap_video_timings *timings) in hdmi_wp_video_config_interface() argument
152 vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; in hdmi_wp_video_config_interface()
153 hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; in hdmi_wp_video_config_interface()
158 r = FLD_MOD(r, timings->interlace, 3, 3); in hdmi_wp_video_config_interface()
164 struct omap_video_timings *timings) in hdmi_wp_video_config_timing() argument
171 timing_h |= FLD_VAL(timings->hbp, 31, 20); in hdmi_wp_video_config_timing()
172 timing_h |= FLD_VAL(timings->hfp, 19, 8); in hdmi_wp_video_config_timing()
173 timing_h |= FLD_VAL(timings->hsw, 7, 0); in hdmi_wp_video_config_timing()
176 timing_v |= FLD_VAL(timings->vbp, 31, 20); in hdmi_wp_video_config_timing()
177 timing_v |= FLD_VAL(timings->vfp, 19, 8); in hdmi_wp_video_config_timing()
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Dhdmi5_core.c297 video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level; in hdmi_core_init()
298 video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res; in hdmi_core_init()
299 video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1; in hdmi_core_init()
300 video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp; in hdmi_core_init()
301 video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp; in hdmi_core_init()
302 video_cfg->hblank = cfg->timings.hfp + in hdmi_core_init()
303 cfg->timings.hbp + cfg->timings.hsw - 1; in hdmi_core_init()
304 video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level; in hdmi_core_init()
305 video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res; in hdmi_core_init()
306 video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw; in hdmi_core_init()
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Dvenc.c305 struct omap_video_timings timings; member
420 struct omap_video_timings *timings) in venc_timings_to_config() argument
422 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) in venc_timings_to_config()
425 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) in venc_timings_to_config()
443 venc_write_config(venc_timings_to_config(&venc.timings)); in venc_power_on()
460 dss_mgr_set_timings(mgr, &venc.timings); in venc_power_on()
538 struct omap_video_timings *timings) in venc_set_timings() argument
545 if (memcmp(&venc.timings, timings, sizeof(*timings))) in venc_set_timings()
548 venc.timings = *timings; in venc_set_timings()
556 struct omap_video_timings *timings) in venc_check_timings() argument
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/drivers/video/fbdev/core/
Dfbmon.c1146 static void fb_timings_vfreq(struct __fb_timings *timings) in fb_timings_vfreq() argument
1148 timings->hfreq = fb_get_hfreq(timings->vfreq, timings->vactive); in fb_timings_vfreq()
1149 timings->vblank = fb_get_vblank(timings->hfreq); in fb_timings_vfreq()
1150 timings->vtotal = timings->vactive + timings->vblank; in fb_timings_vfreq()
1151 timings->hblank = fb_get_hblank_by_hfreq(timings->hfreq, in fb_timings_vfreq()
1152 timings->hactive); in fb_timings_vfreq()
1153 timings->htotal = timings->hactive + timings->hblank; in fb_timings_vfreq()
1154 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1157 static void fb_timings_hfreq(struct __fb_timings *timings) in fb_timings_hfreq() argument
1159 timings->vblank = fb_get_vblank(timings->hfreq); in fb_timings_hfreq()
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/drivers/media/rc/
Drc-ir-raw.c248 const struct ir_raw_timings_manchester *timings, in ir_raw_gen_manchester() argument
257 if (timings->leader) { in ir_raw_gen_manchester()
260 if (timings->pulse_space_start) { in ir_raw_gen_manchester()
261 init_ir_raw_event_duration((*ev)++, 1, timings->leader); in ir_raw_gen_manchester()
265 init_ir_raw_event_duration((*ev), 0, timings->leader); in ir_raw_gen_manchester()
267 init_ir_raw_event_duration((*ev), 1, timings->leader); in ir_raw_gen_manchester()
278 if (timings->invert) in ir_raw_gen_manchester()
281 (*ev)->duration += timings->clock; in ir_raw_gen_manchester()
286 timings->clock); in ir_raw_gen_manchester()
292 timings->clock); in ir_raw_gen_manchester()
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/drivers/media/i2c/adv748x/
Dadv748x-hdmi.c52 struct v4l2_dv_timings timings; member
100 fmt->field = hdmi->timings.bt.interlaced ? in adv748x_hdmi_fill_format()
106 fmt->width = hdmi->timings.bt.width; in adv748x_hdmi_fill_format()
107 fmt->height = hdmi->timings.bt.height; in adv748x_hdmi_fill_format()
113 static void adv748x_fill_optional_dv_timings(struct v4l2_dv_timings *timings) in adv748x_fill_optional_dv_timings() argument
115 v4l2_find_dv_timings_cap(timings, &adv748x_hdmi_timings_cap, in adv748x_fill_optional_dv_timings()
176 const struct v4l2_dv_timings *timings) in adv748x_hdmi_set_video_timings() argument
183 if (!v4l2_match_dv_timings(timings, &stds[i].timings, 250000, in adv748x_hdmi_set_video_timings()
222 struct v4l2_dv_timings *timings) in adv748x_hdmi_s_dv_timings() argument
228 if (!timings) in adv748x_hdmi_s_dv_timings()
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/drivers/video/fbdev/omap2/omapfb/displays/
Dencoder-tfp410.c27 struct omap_video_timings timings; member
84 in->ops.dpi->set_timings(in, &ddata->timings); in tfp410_enable()
116 static void tfp410_fix_timings(struct omap_video_timings *timings) in tfp410_fix_timings() argument
118 timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; in tfp410_fix_timings()
119 timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; in tfp410_fix_timings()
120 timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH; in tfp410_fix_timings()
124 struct omap_video_timings *timings) in tfp410_set_timings() argument
129 tfp410_fix_timings(timings); in tfp410_set_timings()
131 ddata->timings = *timings; in tfp410_set_timings()
132 dssdev->panel.timings = *timings; in tfp410_set_timings()
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Dconnector-analog-tv.c26 struct omap_video_timings timings; member
94 in->ops.atv->set_timings(in, &ddata->timings); in tvc_enable()
128 struct omap_video_timings *timings) in tvc_set_timings() argument
133 ddata->timings = *timings; in tvc_set_timings()
134 dssdev->panel.timings = *timings; in tvc_set_timings()
136 in->ops.atv->set_timings(in, timings); in tvc_set_timings()
140 struct omap_video_timings *timings) in tvc_get_timings() argument
144 *timings = ddata->timings; in tvc_get_timings()
148 struct omap_video_timings *timings) in tvc_check_timings() argument
153 return in->ops.atv->check_timings(in, timings); in tvc_check_timings()
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Dconnector-hdmi.c45 struct omap_video_timings timings; member
97 in->ops.hdmi->set_timings(in, &ddata->timings); in hdmic_enable()
124 struct omap_video_timings *timings) in hdmic_set_timings() argument
129 ddata->timings = *timings; in hdmic_set_timings()
130 dssdev->panel.timings = *timings; in hdmic_set_timings()
132 in->ops.hdmi->set_timings(in, timings); in hdmic_set_timings()
136 struct omap_video_timings *timings) in hdmic_get_timings() argument
140 *timings = ddata->timings; in hdmic_get_timings()
144 struct omap_video_timings *timings) in hdmic_check_timings() argument
149 return in->ops.hdmi->check_timings(in, timings); in hdmic_check_timings()
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Dconnector-dvi.c46 struct omap_video_timings timings; member
92 in->ops.dvi->set_timings(in, &ddata->timings); in dvic_enable()
117 struct omap_video_timings *timings) in dvic_set_timings() argument
122 ddata->timings = *timings; in dvic_set_timings()
123 dssdev->panel.timings = *timings; in dvic_set_timings()
125 in->ops.dvi->set_timings(in, timings); in dvic_set_timings()
129 struct omap_video_timings *timings) in dvic_get_timings() argument
133 *timings = ddata->timings; in dvic_get_timings()
137 struct omap_video_timings *timings) in dvic_check_timings() argument
142 return in->ops.dvi->check_timings(in, timings); in dvic_check_timings()
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Dencoder-opa362.c31 struct omap_video_timings timings; member
94 in->ops.atv->set_timings(in, &ddata->timings); in opa362_enable()
127 struct omap_video_timings *timings) in opa362_set_timings() argument
134 ddata->timings = *timings; in opa362_set_timings()
135 dssdev->panel.timings = *timings; in opa362_set_timings()
137 in->ops.atv->set_timings(in, timings); in opa362_set_timings()
141 struct omap_video_timings *timings) in opa362_get_timings() argument
147 *timings = ddata->timings; in opa362_get_timings()
151 struct omap_video_timings *timings) in opa362_check_timings() argument
158 return in->ops.atv->check_timings(in, timings); in opa362_check_timings()
Dencoder-tpd12s015.c29 struct omap_video_timings timings; member
85 in->ops.hdmi->set_timings(in, &ddata->timings); in tpd_enable()
110 struct omap_video_timings *timings) in tpd_set_timings() argument
115 ddata->timings = *timings; in tpd_set_timings()
116 dssdev->panel.timings = *timings; in tpd_set_timings()
118 in->ops.hdmi->set_timings(in, timings); in tpd_set_timings()
122 struct omap_video_timings *timings) in tpd_get_timings() argument
126 *timings = ddata->timings; in tpd_get_timings()
130 struct omap_video_timings *timings) in tpd_check_timings() argument
136 r = in->ops.hdmi->check_timings(in, timings); in tpd_check_timings()
/drivers/ide/
Dcs5536.c149 unsigned long timings = (unsigned long)ide_get_drivedata(drive); in cs5536_set_pio_mode() local
157 timings &= (IDE_DRV_MASK << 8); in cs5536_set_pio_mode()
158 timings |= drv_timings[pio]; in cs5536_set_pio_mode()
159 ide_set_drivedata(drive, (void *)timings); in cs5536_set_pio_mode()
192 unsigned long timings = (unsigned long)ide_get_drivedata(drive); in cs5536_set_dma_mode() local
203 timings &= IDE_DRV_MASK; in cs5536_set_dma_mode()
204 timings |= mwdma_timings[mode - XFER_MW_DMA_0] << 8; in cs5536_set_dma_mode()
205 ide_set_drivedata(drive, (void *)timings); in cs5536_set_dma_mode()
213 unsigned long timings = (unsigned long)ide_get_drivedata(drive); in cs5536_dma_start() local
216 (timings >> 8) != (timings & IDE_DRV_MASK)) in cs5536_dma_start()
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Dcs5530.c39 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132) argument
106 unsigned int reg, timings = 0; in cs5530_set_dma_mode() local
109 case XFER_UDMA_0: timings = 0x00921250; break; in cs5530_set_dma_mode()
110 case XFER_UDMA_1: timings = 0x00911140; break; in cs5530_set_dma_mode()
111 case XFER_UDMA_2: timings = 0x00911030; break; in cs5530_set_dma_mode()
112 case XFER_MW_DMA_0: timings = 0x00077771; break; in cs5530_set_dma_mode()
113 case XFER_MW_DMA_1: timings = 0x00012121; break; in cs5530_set_dma_mode()
114 case XFER_MW_DMA_2: timings = 0x00002020; break; in cs5530_set_dma_mode()
118 timings |= reg & 0x80000000; /* preserve PIO format bit */ in cs5530_set_dma_mode()
120 outl(timings, basereg + 4); /* write drive0 config register */ in cs5530_set_dma_mode()
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Dpmac.c64 u32 timings[4]; member
421 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG)); in pmac_ide_apply_timings()
423 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG)); in pmac_ide_apply_timings()
438 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); in pmac_ide_kauai_apply_timings()
439 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); in pmac_ide_kauai_apply_timings()
441 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); in pmac_ide_kauai_apply_timings()
442 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); in pmac_ide_kauai_apply_timings()
502 u32 *timings, t; in pmac_ide_set_pio_mode() local
508 timings = &pmif->timings[drive->dn & 1]; in pmac_ide_set_pio_mode()
509 t = *timings; in pmac_ide_set_pio_mode()
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/drivers/mtd/nand/
Dnand_timings.c20 .timings.sdr = {
62 .timings.sdr = {
104 .timings.sdr = {
146 .timings.sdr = {
188 .timings.sdr = {
230 .timings.sdr = {
281 return &onfi_sdr_timings[mode].timings.sdr; in onfi_async_timing_mode_to_sdr_timings()
311 struct nand_sdr_timings *timings = &iface->timings.sdr; in onfi_init_data_interface() local
314 timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog); in onfi_init_data_interface()
315 timings->tBERS_max = 1000000ULL * le16_to_cpu(params->t_bers); in onfi_init_data_interface()
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/drivers/media/spi/
Dgs1662.c221 static int gs_status_format(u16 status, struct v4l2_dv_timings *timings) in gs_status_format() argument
228 *timings = reg_fmt[i].format; in gs_status_format()
236 static u16 get_register_timings(struct v4l2_dv_timings *timings) in get_register_timings() argument
241 if (v4l2_match_dv_timings(timings, &reg_fmt[i].format, 0, in get_register_timings()
255 struct v4l2_dv_timings *timings) in gs_s_dv_timings() argument
260 reg_value = get_register_timings(timings); in gs_s_dv_timings()
264 gs->current_timings = *timings; in gs_s_dv_timings()
269 struct v4l2_dv_timings *timings) in gs_g_dv_timings() argument
273 *timings = gs->current_timings; in gs_g_dv_timings()
278 struct v4l2_dv_timings *timings) in gs_query_dv_timings() argument
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/drivers/media/i2c/
Dtvp7002.c328 struct v4l2_dv_timings timings; member
568 const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt; in tvp7002_s_dv_timings()
583 *dv_timings = device->current_timings->timings; in tvp7002_g_dv_timings()
619 const struct tvp7002_timings_definition *timings = tvp7002_timings; in tvp7002_query_dv() local
651 for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++) in tvp7002_query_dv()
652 if (lpfr == timings->lines_per_frame && in tvp7002_query_dv()
653 progressive == timings->progressive) { in tvp7002_query_dv()
654 if (timings->cpl_min == 0xffff) in tvp7002_query_dv()
656 if (cpln >= timings->cpl_min && cpln <= timings->cpl_max) in tvp7002_query_dv()
672 struct v4l2_dv_timings *timings) in tvp7002_query_dv_timings() argument
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/drivers/ata/
Dpata_efar.c99 u8 timings[][2] = { { 0, 0 }, in efar_set_piomode() local
121 master_data |= (timings[pio][0] << 12) | in efar_set_piomode()
122 (timings[pio][1] << 8); in efar_set_piomode()
133 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift; in efar_set_piomode()
168 u8 timings[][2] = { { 0, 0 }, in efar_set_dmamode() local
219 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); in efar_set_dmamode()
226 (timings[pio][0] << 12) | in efar_set_dmamode()
227 (timings[pio][1] << 8); in efar_set_dmamode()
Dpata_it8213.c88 u8 timings[][2] = { { 0, 0 }, in it8213_set_piomode() local
108 master_data |= (timings[pio][0] << 12) | in it8213_set_piomode()
109 (timings[pio][1] << 8); in it8213_set_piomode()
119 slave_data |= (timings[pio][0] << 2) | timings[pio][1]; in it8213_set_piomode()
148 u8 timings[][2] = { { 0, 0 }, in it8213_set_dmamode() local
214 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); in it8213_set_dmamode()
221 (timings[pio][0] << 12) | in it8213_set_dmamode()
222 (timings[pio][1] << 8); in it8213_set_dmamode()
Dpata_rdc.c115 u8 timings[][2] = { { 0, 0 }, in rdc_set_piomode() local
146 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) in rdc_set_piomode()
155 (timings[pio][0] << 12) | in rdc_set_piomode()
156 (timings[pio][1] << 8); in rdc_set_piomode()
194 u8 timings[][2] = { { 0, 0 }, in rdc_set_dmamode() local
268 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); in rdc_set_dmamode()
275 (timings[pio][0] << 12) | in rdc_set_dmamode()
276 (timings[pio][1] << 8); in rdc_set_dmamode()
/drivers/media/rc/img-ir/
Dimg-ir-hw.c88 static void img_ir_timings_preprocess(struct img_ir_timings *timings, in img_ir_timings_preprocess() argument
91 img_ir_symbol_timing_preprocess(&timings->ldr, unit); in img_ir_timings_preprocess()
92 img_ir_symbol_timing_preprocess(&timings->s00, unit); in img_ir_timings_preprocess()
93 img_ir_symbol_timing_preprocess(&timings->s01, unit); in img_ir_timings_preprocess()
94 img_ir_symbol_timing_preprocess(&timings->s10, unit); in img_ir_timings_preprocess()
95 img_ir_symbol_timing_preprocess(&timings->s11, unit); in img_ir_timings_preprocess()
99 timings->ft.ft_min = (timings->ft.ft_min*unit + 999)/1000; in img_ir_timings_preprocess()
120 static void img_ir_timings_defaults(struct img_ir_timings *timings, in img_ir_timings_defaults() argument
123 img_ir_symbol_timing_defaults(&timings->ldr, &defaults->ldr); in img_ir_timings_defaults()
124 img_ir_symbol_timing_defaults(&timings->s00, &defaults->s00); in img_ir_timings_defaults()
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/drivers/memory/
Demif.c383 const struct lpddr2_timings *timings = NULL; in get_timings_table() local
384 const struct lpddr2_timings *timings_arr = emif->plat_data->timings; in get_timings_table()
400 timings = &timings_arr[i]; in get_timings_table()
404 if (!timings) in get_timings_table()
411 return timings; in get_timings_table()
433 static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings, in get_sdram_tim_1_shdw() argument
439 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; in get_sdram_tim_1_shdw()
443 val = DIV_ROUND_UP(timings->tFAW, t_ck*4); in get_sdram_tim_1_shdw()
445 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck)); in get_sdram_tim_1_shdw()
448 val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1; in get_sdram_tim_1_shdw()
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/drivers/video/fbdev/savage/
Dsavagefb_driver.c146 struct xtimings *timings, in vgaHWInit() argument
151 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT)) in vgaHWInit()
154 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT)) in vgaHWInit()
169 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; in vgaHWInit()
170 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; in vgaHWInit()
171 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; in vgaHWInit()
172 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; in vgaHWInit()
173 reg->CRTC[0x04] = (timings->HSyncStart >> 3); in vgaHWInit()
174 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | in vgaHWInit()
175 (((timings->HSyncEnd >> 3)) & 0x1f); in vgaHWInit()
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/drivers/clk/tegra/
Dclk-emc.c88 struct emc_timing *timings; member
129 if (tegra->timings[i].ram_code != ram_code) in emc_determine_rate()
132 timing = tegra->timings + i; in emc_determine_rate()
136 req->rate = tegra->timings[i - 1].rate; in emc_determine_rate()
283 timing = tegra->timings + i; in get_backup_timing()
289 tegra->timings[timing_index].parent_index]) in get_backup_timing()
294 timing = tegra->timings + i; in get_backup_timing()
300 tegra->timings[timing_index].parent_index]) in get_backup_timing()
329 if (tegra->timings[i].rate == rate && in emc_set_rate()
330 tegra->timings[i].ram_code == ram_code) { in emc_set_rate()
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