| /drivers/iio/common/hid-sensors/ |
| D | hid-sensor-attributes.c | 318 static void adjust_exponent_nano(int *val0, int *val1, int scale0, in adjust_exponent_nano() argument
327 *val0 = scale0 * pow_10(exp); in adjust_exponent_nano()
338 *val0 += res; in adjust_exponent_nano()
343 *val0 = *val1 = 0; in adjust_exponent_nano()
346 *val0 = scale0 / pow_10(exp); in adjust_exponent_nano()
356 *val0 = scale0; in adjust_exponent_nano()
363 int *val0, int *val1) in hid_sensor_format_scale() argument
368 *val0 = 1; in hid_sensor_format_scale()
376 adjust_exponent_nano(val0, val1, in hid_sensor_format_scale()
491 int val0, val1; in hid_sensor_parse_common_attributes() local
[all …]
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| /drivers/thunderbolt/ |
| D | icm.c | 776 u32 val0, val1; in icm_reset_phy_port() local
794 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
801 state0 = val0 & PHY_PORT_CS1_LINK_STATE_MASK; in icm_reset_phy_port()
810 val0 |= PHY_PORT_CS1_LINK_DISABLE; in icm_reset_phy_port()
811 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
823 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
830 val0 &= ~PHY_PORT_CS1_LINK_DISABLE; in icm_reset_phy_port()
831 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
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| /drivers/net/ethernet/chelsio/cxgb/ |
| D | pm3393.c | 429 t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
432 (mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
446 u32 val0, val1, val2, val3; in pm3393_update_statistics() local
453 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0); in pm3393_update_statistics()
457 ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) | in pm3393_update_statistics()
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| /drivers/misc/sgi-gru/ |
| D | grulib.h | 97 int val0; member
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| D | grufault.c | 883 if (req.val0 < -1 || req.val0 >= GRU_CHIPLETS_PER_HUB || in gru_set_context_option()
889 gts->ts_user_chiplet_id = req.val0; in gru_set_context_option()
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| /drivers/media/usb/gspca/ |
| D | ov519.c | 2916 unsigned char val0, val1; in ov51x_upload_quan_tables() local
2932 val0 = *pYTable++; in ov51x_upload_quan_tables()
2934 val0 &= 0x0f; in ov51x_upload_quan_tables()
2936 val0 |= val1 << 4; in ov51x_upload_quan_tables()
2937 reg_w(sd, reg, val0); in ov51x_upload_quan_tables()
2939 val0 = *pUVTable++; in ov51x_upload_quan_tables()
2941 val0 &= 0x0f; in ov51x_upload_quan_tables()
2943 val0 |= val1 << 4; in ov51x_upload_quan_tables()
2944 reg_w(sd, reg + size, val0); in ov51x_upload_quan_tables()
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| /drivers/gpu/drm/mga/ |
| D | mga_drv.h | 323 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \ argument
329 DMA_WRITE(1, val0); \
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| /drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 377 static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max) in pll_is_valid() argument
379 return (val0 >= (val1 * min) && val0 <= (val1 * max)); in pll_is_valid()
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| /drivers/infiniband/hw/qib/ |
| D | qib_sd7220.c | 1006 #define RXEQ_VAL(elt, adr, val0, val1, val2, val3) \ argument
1007 {RXEQ_INIT_RDESC((elt), (adr)), {(val0), (val1), (val2), (val3)} }
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| /drivers/staging/media/atomisp/i2c/ |
| D | mt9m114.h | 236 u32 val0; member
|