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Searched refs:vmw_write (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/vmwgfx/
Dvmwgfx_ldu.c114 vmw_write(dev_priv, SVGA_REG_NUM_GUEST_DISPLAYS, in vmw_ldu_commit_list()
121 vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, i); in vmw_ldu_commit_list()
122 vmw_write(dev_priv, SVGA_REG_DISPLAY_IS_PRIMARY, !i); in vmw_ldu_commit_list()
123 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_X, crtc->x); in vmw_ldu_commit_list()
124 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, crtc->y); in vmw_ldu_commit_list()
125 vmw_write(dev_priv, SVGA_REG_DISPLAY_WIDTH, crtc->mode.hdisplay); in vmw_ldu_commit_list()
126 vmw_write(dev_priv, SVGA_REG_DISPLAY_HEIGHT, crtc->mode.vdisplay); in vmw_ldu_commit_list()
127 vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID); in vmw_ldu_commit_list()
Dvmwgfx_fifo.c53 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); in vmw_fifo_have_3d()
128 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | in vmw_fifo_init()
130 vmw_write(dev_priv, SVGA_REG_TRACES, 0); in vmw_fifo_init()
148 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); in vmw_fifo_init()
172 vmw_write(dev_priv, SVGA_REG_SYNC, reason); in vmw_fifo_ping_host()
180 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); in vmw_fifo_release()
186 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, in vmw_fifo_release()
188 vmw_write(dev_priv, SVGA_REG_ENABLE, in vmw_fifo_release()
190 vmw_write(dev_priv, SVGA_REG_TRACES, in vmw_fifo_release()
Dvmwgfx_kms.c1744 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch); in vmw_kms_write_svga()
1748 vmw_write(vmw_priv, SVGA_REG_WIDTH, width); in vmw_kms_write_svga()
1749 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height); in vmw_kms_write_svga()
1750 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp); in vmw_kms_write_svga()
1787 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i); in vmw_kms_save_vga()
1793 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID); in vmw_kms_save_vga()
1815 vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width); in vmw_kms_restore_vga()
1816 vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height); in vmw_kms_restore_vga()
1817 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp); in vmw_kms_restore_vga()
1819 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, in vmw_kms_restore_vga()
[all …]
Dvmwgfx_irq.c244 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
255 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
350 vmw_write(dev_priv, SVGA_REG_IRQMASK, 0); in vmw_irq_uninstall()
Dvmwgfx_drv.c678 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); in vmw_driver_load()
740 vmw_write(dev_priv, SVGA_REG_DEV_CAP, in vmw_driver_load()
744 vmw_write(dev_priv, SVGA_REG_DEV_CAP, in vmw_driver_load()
887 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX); in vmw_driver_load()
1303 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); in __vmw_svga_enable()
1333 vmw_write(dev_priv, SVGA_REG_ENABLE, in __vmw_svga_disable()
1369 vmw_write(dev_priv, SVGA_REG_ENABLE, in vmw_svga_disable()
1494 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); in vmw_pm_restore()
Dvmwgfx_ioctl.c162 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); in vmw_fill_compat_cap()
219 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); in vmw_get_cap_3d_ioctl()
Dvmwgfx_cmdbuf.c302 vmw_write(man->dev_priv, SVGA_REG_COMMAND_HIGH, val); in vmw_cmdbuf_header_submit()
306 vmw_write(man->dev_priv, SVGA_REG_COMMAND_LOW, val); in vmw_cmdbuf_header_submit()
Dvmwgfx_drv.h570 static inline void vmw_write(struct vmw_private *dev_priv, in vmw_write() function