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Searched refs:wp (Results 1 – 25 of 46) sorted by relevance

12

/drivers/gpu/drm/omapdrm/dss/
Dhdmi_wp.c23 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
25 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
47 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
49 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
52 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
54 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
56 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
59 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
61 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
64 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
[all …]
Dhdmi.h246 struct hdmi_wp_data *wp; member
299 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
300 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
301 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
302 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
303 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
304 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
305 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
306 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
307 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
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Dhdmi5.c77 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
80 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
81 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
93 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
105 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
108 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
113 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
115 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
200 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); in hdmi_power_on_full()
201 hdmi_wp_set_irqstatus(&hdmi.wp, in hdmi_power_on_full()
[all …]
Dhdmi4.c73 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
76 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
77 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
87 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
89 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
92 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
94 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
96 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
160 struct hdmi_wp_data *wp = &hdmi.wp; in hdmi_power_on_full() local
169 hdmi_wp_clear_irqenable(wp, 0xffffffff); in hdmi_power_on_full()
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Dhdmi_pll.c45 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
53 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
63 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
66 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
149 if (hpll->wp->version == 4) in hdmi_init_pll_data()
164 struct hdmi_wp_data *wp) in hdmi_pll_init() argument
170 pll->wp = wp; in hdmi_pll_init()
Dhdmi4_core.h264 void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
269 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
270 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
271 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
Dhdmi4_core.c310 struct hdmi_wp_data *wp, struct hdmi_config *cfg) in hdmi4_configure() argument
323 hdmi_wp_video_config_timing(wp, &vm); in hdmi4_configure()
328 hdmi_wp_video_config_format(wp, &video_format); in hdmi4_configure()
330 hdmi_wp_video_config_interface(wp, &vm); in hdmi4_configure()
687 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, in hdmi4_audio_config() argument
857 hdmi_wp_audio_config_dma(wp, &audio_dma); in hdmi4_audio_config()
858 hdmi_wp_audio_config_format(wp, &audio_format); in hdmi4_audio_config()
869 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) in hdmi4_audio_start() argument
874 hdmi_wp_audio_core_req_enable(wp, true); in hdmi4_audio_start()
879 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) in hdmi4_audio_stop() argument
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Dhdmi5_core.c609 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, in hdmi5_configure() argument
622 hdmi_wp_video_config_timing(wp, &vm); in hdmi5_configure()
627 hdmi_wp_video_config_format(wp, &video_format); in hdmi5_configure()
629 hdmi_wp_video_config_interface(wp, &vm); in hdmi5_configure()
807 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, in hdmi5_audio_config() argument
896 hdmi_wp_audio_config_dma(wp, &audio_dma); in hdmi5_audio_config()
897 hdmi_wp_audio_config_format(wp, &audio_format); in hdmi5_audio_config()
/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_wp.c22 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
24 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
46 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
48 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
51 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
53 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
55 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
58 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
60 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
63 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
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Dhdmi.h244 struct hdmi_wp_data *wp; member
288 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
289 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
290 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
291 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
292 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
293 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
294 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
295 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
296 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
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Dhdmi5.c76 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
79 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
80 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
92 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
104 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
107 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
112 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
114 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
189 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); in hdmi_power_on_full()
190 hdmi_wp_set_irqstatus(&hdmi.wp, in hdmi_power_on_full()
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Dhdmi4.c72 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
75 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
76 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
86 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
88 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
91 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
93 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
95 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
159 struct hdmi_wp_data *wp = &hdmi.wp; in hdmi_power_on_full() local
167 hdmi_wp_clear_irqenable(wp, 0xffffffff); in hdmi_power_on_full()
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Dhdmi_pll.c104 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
109 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
119 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
121 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
222 struct hdmi_wp_data *wp) in hdmi_pll_init() argument
227 pll->wp = wp; in hdmi_pll_init()
Dhdmi4_core.h264 void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
269 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
270 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
271 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
Dhdmi4_core.c310 struct hdmi_wp_data *wp, struct hdmi_config *cfg) in hdmi4_configure() argument
323 hdmi_wp_video_config_timing(wp, &video_timing); in hdmi4_configure()
328 hdmi_wp_video_config_format(wp, &video_format); in hdmi4_configure()
330 hdmi_wp_video_config_interface(wp, &video_timing); in hdmi4_configure()
687 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, in hdmi4_audio_config() argument
857 hdmi_wp_audio_config_dma(wp, &audio_dma); in hdmi4_audio_config()
858 hdmi_wp_audio_config_format(wp, &audio_format); in hdmi4_audio_config()
869 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) in hdmi4_audio_start() argument
874 hdmi_wp_audio_core_req_enable(wp, true); in hdmi4_audio_start()
879 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) in hdmi4_audio_stop() argument
[all …]
Dhdmi5_core.c600 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, in hdmi5_configure() argument
613 hdmi_wp_video_config_timing(wp, &video_timing); in hdmi5_configure()
618 hdmi_wp_video_config_format(wp, &video_format); in hdmi5_configure()
620 hdmi_wp_video_config_interface(wp, &video_timing); in hdmi5_configure()
798 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, in hdmi5_audio_config() argument
887 hdmi_wp_audio_config_dma(wp, &audio_dma); in hdmi5_audio_config()
888 hdmi_wp_audio_config_format(wp, &audio_format); in hdmi5_audio_config()
/drivers/media/pci/saa7164/
Dsaa7164-core.c367 u32 wp, mcb, rp, cnt = 0; in saa7164_work_enchandler() local
394 wp = saa7164_readl(port->bufcounter); in saa7164_work_enchandler()
395 if (wp > (port->hwcfg.buffercount - 1)) { in saa7164_work_enchandler()
396 printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp); in saa7164_work_enchandler()
401 if (wp == 0) in saa7164_work_enchandler()
404 mcb = wp - 1; in saa7164_work_enchandler()
444 u32 wp, mcb, rp, cnt = 0; in saa7164_work_vbihandler() local
470 wp = saa7164_readl(port->bufcounter); in saa7164_work_vbihandler()
471 if (wp > (port->hwcfg.buffercount - 1)) { in saa7164_work_vbihandler()
472 printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp); in saa7164_work_vbihandler()
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/drivers/net/wireless/realtek/rtlwifi/
Dpci.h326 static inline u16 calc_fifo_space(u16 rp, u16 wp) in calc_fifo_space() argument
328 if (rp <= wp) in calc_fifo_space()
329 return RTL_PCI_MAX_RX_COUNT - 1 + rp - wp; in calc_fifo_space()
330 return rp - wp - 1; in calc_fifo_space()
/drivers/staging/rtlwifi/
Dpci.h322 static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size) in calc_fifo_space() argument
324 if (rp <= wp) in calc_fifo_space()
325 return size - 1 + rp - wp; in calc_fifo_space()
326 return rp - wp - 1; in calc_fifo_space()
/drivers/bus/
Darm-ccn.c963 unsigned long wp = hw->config_base; in arm_ccn_pmu_xp_watchpoint_config() local
970 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); in arm_ccn_pmu_xp_watchpoint_config()
975 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp)); in arm_ccn_pmu_xp_watchpoint_config()
977 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp); in arm_ccn_pmu_xp_watchpoint_config()
979 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp)); in arm_ccn_pmu_xp_watchpoint_config()
981 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp); in arm_ccn_pmu_xp_watchpoint_config()
983 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp)); in arm_ccn_pmu_xp_watchpoint_config()
985 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp); in arm_ccn_pmu_xp_watchpoint_config()
989 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp)); in arm_ccn_pmu_xp_watchpoint_config()
991 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4); in arm_ccn_pmu_xp_watchpoint_config()
[all …]
/drivers/mtd/nand/
Dnandsim.c207 #define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
359 int wp; /* write Protect */ member
878 struct weak_page *wp; in parse_weakpages() local
897 wp = kzalloc(sizeof(*wp), GFP_KERNEL); in parse_weakpages()
898 if (!wp) { in parse_weakpages()
902 wp->page_no = page_no; in parse_weakpages()
903 wp->max_writes = max_writes; in parse_weakpages()
904 list_add(&wp->list, &weak_pages); in parse_weakpages()
911 struct weak_page *wp; in write_error() local
913 list_for_each_entry(wp, &weak_pages, list) in write_error()
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/drivers/block/
Dpktcdvd.c1649 write_param_page *wp; in pkt_set_write_settings() local
1658 init_cdrom_command(&cgc, buffer, sizeof(*wp), CGC_DATA_READ); in pkt_set_write_settings()
1683 wp = (write_param_page *) &buffer[sizeof(struct mode_page_header) + pd->mode_offset]; in pkt_set_write_settings()
1685 wp->fp = pd->settings.fp; in pkt_set_write_settings()
1686 wp->track_mode = pd->settings.track_mode; in pkt_set_write_settings()
1687 wp->write_type = pd->settings.write_type; in pkt_set_write_settings()
1688 wp->data_block_type = pd->settings.block_mode; in pkt_set_write_settings()
1690 wp->multi_session = 0; in pkt_set_write_settings()
1693 wp->link_size = 7; in pkt_set_write_settings()
1694 wp->ls_v = 1; in pkt_set_write_settings()
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/drivers/scsi/qedf/
Dqedf_fip.c152 struct fip_wwn_desc *wp; in qedf_fip_recv() local
205 wp = (struct fip_wwn_desc *)desc; in qedf_fip_recv()
208 get_unaligned_be64(&wp->fd_wwn)); in qedf_fip_recv()
/drivers/media/platform/sti/c8sectpfe/
Dc8sectpfe-core.c87 unsigned long wp, rp; in channel_swdemux_tsklet() local
96 wp = readl(channel->irec + DMA_PRDS_BUSWP_TP(0)); in channel_swdemux_tsklet()
102 if (wp < rp) in channel_swdemux_tsklet()
103 wp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE; in channel_swdemux_tsklet()
105 size = wp - rp; in channel_swdemux_tsklet()
118 channel->tsin_id, channel, num_packets, buf, pos, rp, wp); in channel_swdemux_tsklet()
130 if (wp == (channel->back_buffer_busaddr + FEI_BUFFER_SIZE)) in channel_swdemux_tsklet()
134 writel(wp, channel->irec + DMA_PRDS_BUSRP_TP(0)); in channel_swdemux_tsklet()
/drivers/block/drbd/
Ddrbd_proc.c245 char wp; in drbd_seq_show() local
294 wp = nc ? nc->wire_protocol - DRBD_PROT_A + 'A' : ' '; in drbd_seq_show()
304 wp, in drbd_seq_show()

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