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Searched refs:wptr (Results 1 – 25 of 72) sorted by relevance

123

/drivers/media/usb/pvrusb2/
Dpvrusb2-debugifc.c65 const char *wptr; in debugifc_isolate_word() local
70 wptr = NULL; in debugifc_isolate_word()
78 wptr = buf; in debugifc_isolate_word()
83 *wstrPtr = wptr; in debugifc_isolate_word()
192 const char *wptr; in pvr2_debugifc_do1cmd() local
196 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
199 if (!wptr) return 0; in pvr2_debugifc_do1cmd()
201 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr); in pvr2_debugifc_do1cmd()
202 if (debugifc_match_keyword(wptr,wlen,"reset")) { in pvr2_debugifc_do1cmd()
203 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
[all …]
/drivers/gpu/drm/amd/amdkfd/
Dkfd_interrupt.c111 unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr); in enqueue_ih_ring_entry() local
113 if ((rptr - wptr) % kfd->interrupt_ring_size == in enqueue_ih_ring_entry()
121 memcpy(kfd->interrupt_ring + wptr, ih_ring_entry, in enqueue_ih_ring_entry()
124 wptr = (wptr + kfd->device_info->ih_ring_entry_size) % in enqueue_ih_ring_entry()
127 atomic_set(&kfd->interrupt_ring_wptr, wptr); in enqueue_ih_ring_entry()
143 unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr); in dequeue_ih_ring_entry() local
146 if (rptr == wptr) in dequeue_ih_ring_entry()
Dkfd_kernel_queue.c210 uint32_t wptr, rptr; in acquire_packet_buffer() local
219 wptr = *kq->wptr_kernel; in acquire_packet_buffer()
224 pr_debug("wptr: %d\n", wptr); in acquire_packet_buffer()
227 available_size = (rptr + queue_size_dwords - 1 - wptr) % in acquire_packet_buffer()
239 if (wptr + packet_size_in_dwords >= queue_size_dwords) { in acquire_packet_buffer()
248 while (wptr > 0) { in acquire_packet_buffer()
249 queue_address[wptr] = kq->nop_packet; in acquire_packet_buffer()
250 wptr = (wptr + 1) % queue_size_dwords; in acquire_packet_buffer()
254 *buffer_ptr = &queue_address[wptr]; in acquire_packet_buffer()
255 kq->pending_wptr = wptr + packet_size_in_dwords; in acquire_packet_buffer()
/drivers/net/ppp/
Dbsd_comp.c580 unsigned char *wptr; in bsd_compress() local
586 if (wptr) \ in bsd_compress()
588 *wptr++ = (unsigned char) (v); \ in bsd_compress()
591 wptr = NULL; \ in bsd_compress()
630 wptr = obuf; in bsd_compress()
639 if (wptr) in bsd_compress()
641 *wptr++ = PPP_ADDRESS(rptr); in bsd_compress()
642 *wptr++ = PPP_CONTROL(rptr); in bsd_compress()
643 *wptr++ = 0; in bsd_compress()
644 *wptr++ = PPP_COMP; in bsd_compress()
[all …]
Dppp_deflate.c193 unsigned char *wptr; in z_compress() local
207 wptr = obuf; in z_compress()
212 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
213 wptr[1] = PPP_CONTROL(rptr); in z_compress()
214 put_unaligned_be16(PPP_COMP, wptr + 2); in z_compress()
215 wptr += PPP_HDRLEN; in z_compress()
216 put_unaligned_be16(state->seqno, wptr); in z_compress()
217 wptr += DEFLATE_OVHD; in z_compress()
219 state->strm.next_out = wptr; in z_compress()
/drivers/net/ethernet/tehuti/
Dtehuti.c172 f->wptr = 0; in bdx_fifo_init()
1108 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_rx_alloc_skbs()
1116 f->m.wptr += sizeof(struct rxf_desc); in bdx_rx_alloc_skbs()
1117 delta = f->m.wptr - f->m.memsz; in bdx_rx_alloc_skbs()
1119 f->m.wptr = delta; in bdx_rx_alloc_skbs()
1128 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); in bdx_rx_alloc_skbs()
1165 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_recycle_skb()
1173 f->m.wptr += sizeof(struct rxf_desc); in bdx_recycle_skb()
1174 delta = f->m.wptr - f->m.memsz; in bdx_recycle_skb()
1176 f->m.wptr = delta; in bdx_recycle_skb()
[all …]
/drivers/gpu/drm/radeon/
Dradeon_ring.c84 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size()
125 ring->wptr_old = ring->wptr; in radeon_ring_alloc()
173 while (ring->wptr & ring->align_mask) { in radeon_ring_commit()
211 ring->wptr = ring->wptr_old; in radeon_ring_undo()
308 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup()
468 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info() local
474 wptr = radeon_ring_get_wptr(rdev, ring); in radeon_debugfs_ring_info()
476 wptr, wptr); in radeon_debugfs_ring_info()
490 ring->wptr, ring->wptr); in radeon_debugfs_ring_info()
Dvce_v1_0.c97 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
99 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
298 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
299 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start()
305 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start()
306 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
/drivers/gpu/drm/amd/amdgpu/
Diceland_ih.c190 u32 wptr, tmp; in iceland_ih_get_wptr() local
192 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in iceland_ih_get_wptr()
194 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in iceland_ih_get_wptr()
195 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in iceland_ih_get_wptr()
201 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in iceland_ih_get_wptr()
202 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in iceland_ih_get_wptr()
207 return (wptr & adev->irq.ih.ptr_mask); in iceland_ih_get_wptr()
Dcz_ih.c190 u32 wptr, tmp; in cz_ih_get_wptr() local
192 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in cz_ih_get_wptr()
194 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in cz_ih_get_wptr()
195 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in cz_ih_get_wptr()
201 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in cz_ih_get_wptr()
202 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in cz_ih_get_wptr()
207 return (wptr & adev->irq.ih.ptr_mask); in cz_ih_get_wptr()
Damdgpu_amdkfd.h65 #define read_user_wptr(mmptr, wptr, dst) \ argument
68 if ((mmptr) && (wptr)) { \
70 valid = !get_user((dst), (wptr)); \
73 valid = !get_user((dst), (wptr)); \
Damdgpu_ih.c152 u32 wptr; in amdgpu_ih_process() local
157 wptr = amdgpu_ih_get_wptr(adev); in amdgpu_ih_process()
164 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr); in amdgpu_ih_process()
169 while (adev->irq.ih.rptr != wptr) { in amdgpu_ih_process()
187 wptr = amdgpu_ih_get_wptr(adev); in amdgpu_ih_process()
188 if (wptr != adev->irq.ih.rptr) in amdgpu_ih_process()
Dsi_ih.c105 u32 wptr, tmp; in si_ih_get_wptr() local
107 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in si_ih_get_wptr()
109 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in si_ih_get_wptr()
110 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in si_ih_get_wptr()
112 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in si_ih_get_wptr()
113 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in si_ih_get_wptr()
118 return (wptr & adev->irq.ih.ptr_mask); in si_ih_get_wptr()
Dcik_ih.c188 u32 wptr, tmp; in cik_ih_get_wptr() local
190 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in cik_ih_get_wptr()
192 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in cik_ih_get_wptr()
193 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in cik_ih_get_wptr()
199 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in cik_ih_get_wptr()
200 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in cik_ih_get_wptr()
205 return (wptr & adev->irq.ih.ptr_mask); in cik_ih_get_wptr()
Dtonga_ih.c198 u32 wptr, tmp; in tonga_ih_get_wptr() local
201 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); in tonga_ih_get_wptr()
203 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in tonga_ih_get_wptr()
205 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in tonga_ih_get_wptr()
206 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in tonga_ih_get_wptr()
212 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in tonga_ih_get_wptr()
213 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in tonga_ih_get_wptr()
218 return (wptr & adev->irq.ih.ptr_mask); in tonga_ih_get_wptr()
Dvega10_ih.c203 u32 wptr, tmp; in vega10_ih_get_wptr() local
206 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); in vega10_ih_get_wptr()
208 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in vega10_ih_get_wptr()
210 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in vega10_ih_get_wptr()
211 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in vega10_ih_get_wptr()
217 tmp = (wptr + 32) & adev->irq.ih.ptr_mask; in vega10_ih_get_wptr()
219 wptr, adev->irq.ih.rptr, tmp); in vega10_ih_get_wptr()
226 return (wptr & adev->irq.ih.ptr_mask); in vega10_ih_get_wptr()
Dsdma_v4_0.c254 u64 *wptr = NULL; in sdma_v4_0_ring_get_wptr() local
259 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); in sdma_v4_0_ring_get_wptr()
260 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); in sdma_v4_0_ring_get_wptr()
261 *wptr = (*wptr) >> 2; in sdma_v4_0_ring_get_wptr()
262 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); in sdma_v4_0_ring_get_wptr()
267 wptr = &local_wptr; in sdma_v4_0_ring_get_wptr()
273 *wptr = highbit; in sdma_v4_0_ring_get_wptr()
274 *wptr = (*wptr) << 32; in sdma_v4_0_ring_get_wptr()
275 *wptr |= lowbit; in sdma_v4_0_ring_get_wptr()
278 return *wptr; in sdma_v4_0_ring_get_wptr()
[all …]
Damdgpu_ring.h162 u64 wptr; member
219 ring->ring[ring->wptr++ & ring->buf_mask] = v; in amdgpu_ring_write()
220 ring->wptr &= ring->ptr_mask; in amdgpu_ring_write()
233 occupied = ring->wptr & ring->buf_mask; in amdgpu_ring_write_multiple()
250 ring->wptr += count_dw; in amdgpu_ring_write_multiple()
251 ring->wptr &= ring->ptr_mask; in amdgpu_ring_write_multiple()
Dvce_v4_0.c106 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()
107 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
113 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
116 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
119 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
178 adev->vce.ring[0].wptr = 0; in vce_v4_0_mmsch_start()
323 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
324 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
331 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start()
332 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start()
[all …]
/drivers/infiniband/hw/cxgb3/
Dcxio_hal.c606 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len, in cxio_hal_ctrl_qp_write_mem()
610 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
614 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i); in cxio_hal_ctrl_qp_write_mem()
617 rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
626 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % in cxio_hal_ctrl_qp_write_mem()
668 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % in cxio_hal_ctrl_qp_write_mem()
672 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr; in cxio_hal_ctrl_qp_write_mem()
679 Q_GENBIT(rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
685 rdev_p->ctrl_qp.wptr++; in cxio_hal_ctrl_qp_write_mem()
703 u32 wptr; in __cxio_tpt_op() local
[all …]
Dcxio_wr.h46 #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr)) argument
47 #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \ argument
48 ((rptr)!=(wptr)) )
50 #define Q_FREECNT(rptr,wptr,size_log2) ((1UL<<size_log2)-((wptr)-(rptr))) argument
51 #define Q_COUNT(rptr,wptr) ((wptr)-(rptr)) argument
697 u32 wptr; /* idx to next available WR slot */ member
718 u32 wptr; member
/drivers/video/fbdev/
Dmaxinefb.c67 unsigned char *wptr; in maxinefb_ims332_write_register() local
69 wptr = regs + 0xa0000 + (regno << 4); in maxinefb_ims332_write_register()
71 *((volatile unsigned short *) (wptr)) = val; in maxinefb_ims332_write_register()
/drivers/gpu/drm/msm/adreno/
Dadreno_gpu.c224 uint32_t wptr; in adreno_flush() local
231 wptr = get_wptr(gpu->rb) & ((gpu->rb->size / 4) - 1); in adreno_flush()
236 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); in adreno_flush()
242 uint32_t wptr = get_wptr(gpu->rb); in adreno_idle() local
245 if (!spin_until(get_rptr(adreno_gpu) == wptr)) in adreno_idle()
329 uint32_t wptr = get_wptr(gpu->rb); in ring_freewords() local
331 return (rptr + (size - 1) - wptr) % size; in ring_freewords()
/drivers/scsi/qla2xxx/
Dqla_sup.c550 uint16_t cnt, chksum, *wptr; in qla2xxx_find_flt_start() local
611 wptr = (uint16_t *)req->ring; in qla2xxx_find_flt_start()
613 for (chksum = 0; cnt--; wptr++) in qla2xxx_find_flt_start()
614 chksum += le16_to_cpu(*wptr); in qla2xxx_find_flt_start()
668 uint16_t *wptr; in qla2xxx_get_flt_info() local
689 wptr = (uint16_t *)req->ring; in qla2xxx_get_flt_info()
694 if (*wptr == cpu_to_le16(0xffff)) in qla2xxx_get_flt_info()
705 for (chksum = 0; cnt--; wptr++) in qla2xxx_get_flt_info()
706 chksum += le16_to_cpu(*wptr); in qla2xxx_get_flt_info()
916 uint16_t *wptr; in qla2xxx_get_fdt_info() local
[all …]
/drivers/tty/serial/
Dmen_z135_uart.c301 u32 wptr; in men_z135_handle_tx() local
323 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); in men_z135_handle_tx()
324 txc = (wptr >> 16) & 0x3ff; in men_z135_handle_tx()
325 wptr &= 0x3ff; in men_z135_handle_tx()
341 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr)) in men_z135_handle_tx()
342 n = 4 - BYTES_TO_ALIGN(wptr); in men_z135_handle_tx()
463 u32 wptr; in men_z135_tx_empty() local
466 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); in men_z135_tx_empty()
467 txc = (wptr >> 16) & 0x3ff; in men_z135_tx_empty()

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